公开(公告)号：JP2002215706A

公开(公告)日：2002-08-02

申请号：JP2001338435

申请日：2001-11-02

Applicant: IBM

Inventor： COHN JOHN M ,  DEAN ALVAR A ,  HATHAWAY DAVID J ,  LACKEY DAVID E ,  LEPSIC THOMAS M ,  LICHTENSTEIGER SUSAN K ,  TETREAULT SCOTT A ,  VENTRONE SEBASTIAN T

IPC: G06F17/50 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide a logical and physical constitution for a voltage island. SOLUTION: In design of a semiconductor chip, it is parted by the unit of bin, which means plural ranges in the design. Design of one semiconductor chip can thus be sliced to various ranges, and these ranges can be allotted to various voltage levels. Each bin can be regarded as one voltage island. Circuits in the design can be added to various bins, or eliminated from the various bins. Circuit speed and power can be increased or reduced by this. When the circuit is disposed in the bin to which a high voltage is allotted, speed and power are increased. When the circuit is disposed in the bin having a low voltage, speed and power are reduced. The size and position of the bin can also be changed. By repeating these steps, the optimum power consumption can be achieved while satisfying other standards such as constraint related to speed.

公开(公告)号：JP2002328962A

公开(公告)日：2002-11-15

申请号：JP2002031625

申请日：2002-02-08

Applicant: IBM

Inventor： COHN JOHN M ,  DEAN ALVAR A ,  AMIR H FARRAHI ,  HATHAWAY DAVID J ,  THOMAS M RESHIKKU ,  JAGANATHAN NAGASHIMAAN ,  SCOTT A TETORAATO ,  VENTRONE SEBASTIAN T

IPC: G06F17/50 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure which reduces power consumption on a microelectronic circuit. SOLUTION: This method distinguishes at least one wiring pair including the first wiring and the second wiring. The second wiring is already tristated or tristatable. The wiring pair has same directional probability over the prescribed or the user selected minimum same directional switching availability for one clock cycle. Or, the wiring pair has opposite directional probability over the prescribed or the user selected minimum opposite directional switching availability for one clock cycle. The first and the second wiring satisfies at least one mathematical relation, and this mathematical relation includes distance between the first and the second wiring, and common run length of the first and the second wiring.

公开(公告)号：JP2002230066A

公开(公告)日：2002-08-16

申请号：JP2001369057

申请日：2001-12-03

Applicant: IBM

Inventor： COHN JOHN M ,  DEAN ALVAR A ,  HATHAWAY DAVID J ,  VENTRONE SEBASTIAN T

IPC: G06F17/50 ,  G06F1/32

Abstract: PROBLEM TO BE SOLVED: To provide a logic system designing method for reducing leak by forcing the sate of a logical gate based on probabilistic analysis. SOLUTION: This method for reducing the leak power of a logical network comprises a step for identifying the 'sleep state' of each net by using observability don't care information, a step for determing at least one net in which expected power consumption is reduced by forcing a net to a specific value during at least a part of the sleep state based on probabilistic analysis, and a step for forcing the determined net to the determined value during the determined part of the sleep state.