公开(公告)号：EP1665344A4

公开(公告)日：2007-07-18

申请号：EP04784950

申请日：2004-09-24

Applicant: IBM

Inventor： GOODNOW KENNETH J ,  KAMPF FRANCIS A ,  NORMAN JASON M ,  VENTRONE SEBASTIAN T

IPC: G06F13/16 ,  G06F12/02

CPC classification number: G06F12/0284

Abstract: A structure and method of transferring data on a semiconductor device (2) having a plurality of systems (e.g. 6 and 3). Each system has at least one processing device (e.g. 7) and a local memory structure (e.g. 8). Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

公开(公告)号：EP1573553A4

公开(公告)日：2007-11-21

申请号：EP02795913

申请日：2002-12-17

Applicant: IBM

Inventor： BLANCO RAFAEL ,  SMITH JACK R ,  VENTRONE SEBASTIAN T

IPC: G06F12/08

CPC classification number: G06F12/0886 ,  G06F12/0864

Abstract: The invention provides for selectively changing a line width for a memory, i.e., selecting one of a plurality of line widths for a memory (14). The selected line width is used in communicating with one or more processors (12, 26). This provides increased flexibility and efficiency for communicating with the memory. In particular, a register (42) can be set based on a desired line width, and subsequently used when locating data in the memory. The selected line width can be associated with each data block (38) in the memory to allow multiple line widths to be used simultaneously. When implemented in a cache (30, 130), multiple ways (40) of the cache can be processed as a group to provide data during a single memory operation. The line width can be varied based on a task (13, 28), a processor, and/or a performance evaluation.

Abstract translation: 本发明提供了选择性地改变存储器的线宽，即为存储器（14）选择多个线宽中的一个。 选定的线宽用于与一个或多个处理器（12,26）通信。 这为与内存进行通信提供了更高的灵活性和效率。 具体地说，寄存器（42）可以基于期望的线宽设置，并且随后在将数据定位在存储器中时使用。 选定的行宽可以与存储器中的每个数据块（38）相关联以允许同时使用多个行宽度。 当在高速缓存（30,130）中实现时，可以将高速缓存的多个路（40）作为一组处理，以在单个存储器操作期间提供数据。 线宽可以根据任务（13,28），处理器和/或性能评估而变化。

公开(公告)号：JP2006023859A

公开(公告)日：2006-01-26

申请号：JP2004199833

申请日：2004-07-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SMITH JACK R ,  VENTRONE SEBASTIAN T

IPC: G06F17/50 ,  H03K19/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for designing an integrated circuit having latches.
SOLUTION: The logic design of logic elements and latches is prepared and the logic elements and the latches are positioned within the integrated circuit according to the logic design in order to create a physical design. During the process of creating the physical design, the latches that do not transition into the same clock cycle, the latches unrelated to the same logic function, the latches within the same clock domain, and the latches in a given physical proximity to each other are combined in order to delete any redundant latches. This process of deleting the redundant latches includes replacing at least two of the latches by a single latch. The physical design is corrected through the process of deleting the redundant latches and a test is conducted on the corrected physical design to determine whether the corrected physical design will operate as expected.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于设计具有闩锁的集成电路的方法。 解决方案：根据逻辑设计准备逻辑元件和锁存器的逻辑设计，逻辑元件和锁存器位于集成电路内，以创建物理设计。 在创建物理设计的过程中，不转换到相同时钟周期的锁存器，与相同逻辑功能无关的锁存器，同一时钟域内的锁存器和彼此给定的物理接近的锁存器是 组合以删除任何冗余锁存器。 删除冗余锁存器的这个过程包括通过单个锁存器替换至少两个锁存器。 通过删除冗余锁存器的过程来校正物理设计，并对修正的物理设计进行测试，以确定校正的物理设计是否按预期运行。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2002215706A

公开(公告)日：2002-08-02

申请号：JP2001338435

申请日：2001-11-02

Applicant: IBM

Inventor： COHN JOHN M ,  DEAN ALVAR A ,  HATHAWAY DAVID J ,  LACKEY DAVID E ,  LEPSIC THOMAS M ,  LICHTENSTEIGER SUSAN K ,  TETREAULT SCOTT A ,  VENTRONE SEBASTIAN T

IPC: G06F17/50 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide a logical and physical constitution for a voltage island. SOLUTION: In design of a semiconductor chip, it is parted by the unit of bin, which means plural ranges in the design. Design of one semiconductor chip can thus be sliced to various ranges, and these ranges can be allotted to various voltage levels. Each bin can be regarded as one voltage island. Circuits in the design can be added to various bins, or eliminated from the various bins. Circuit speed and power can be increased or reduced by this. When the circuit is disposed in the bin to which a high voltage is allotted, speed and power are increased. When the circuit is disposed in the bin having a low voltage, speed and power are reduced. The size and position of the bin can also be changed. By repeating these steps, the optimum power consumption can be achieved while satisfying other standards such as constraint related to speed.

公开(公告)号：EP1644964A4

公开(公告)日：2008-07-30

申请号：EP04778016

申请日：2004-07-09

Applicant: IBM

Inventor： BLANCO RAFAEL ,  COHN JOHN M ,  GOODNOW KENNETH J ,  STOUT DOUGLAS W ,  VENTRONE SEBASTIAN T

IPC: G11C16/04 ,  G06F1/32 ,  G11C5/14 ,  G11C19/08 ,  H01L20060101

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y02D10/171

Abstract: A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

公开(公告)号：EP1639655A4

公开(公告)日：2008-03-05

申请号：EP04777407

申请日：2004-07-01

Applicant: IBM

Inventor： HORTON ROBERT S ,  MILTON DAVID W ,  OGILVIE CLARENCE R ,  SCHANELY PAUL M ,  VENTRONE SEBASTIAN T

IPC: G06F13/42 ,  H01L31/107 ,  H04L25/14

CPC classification number: G06F13/4247 ,  H04L25/14

Abstract: The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment (120) of a segmented data line (120-122) and then propagating the first data portion along a second segment (121) of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line. The invention breaks a single data transmission into such different data portions and later reassembles the different data portions back into the single data transmission after all of the different data portions have been individually transmitted along all portions of the segmented data line.

公开(公告)号：EP1673867A4

公开(公告)日：2007-07-18

申请号：EP04795023

申请日：2004-10-13

Applicant: IBM

Inventor： GOODNOW KENNETH J ,  OGILVIE CLARENCE R ,  REYNOLDS CHRISTOPHER B ,  SMITH JACK R ,  VENTRONE SEBASTIAN T

IPC: H03K19/173 ,  G06F15/78 ,  H03K19/177

CPC classification number: H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

公开(公告)号：WO2007139536A3

公开(公告)日：2009-05-07

申请号：PCT/US2006020462

申请日：2006-05-21

Applicant: IBM ,  COURCHESNE ADAM J ,  GOODNOW KENNETH J ,  HARDING W RIYON ,  MILTON DAVID W ,  NORMAN JASON M ,  OGILVIE CLARENCE R ,  ROTTELLA JASON E ,  SCHANELY PAUL M ,  VENTRONE SEBASTIAN T

Inventor： COURCHESNE ADAM J ,  GOODNOW KENNETH J ,  HARDING W RIYON ,  MILTON DAVID W ,  NORMAN JASON M ,  OGILVIE CLARENCE R ,  ROTTELLA JASON E ,  SCHANELY PAUL M ,  VENTRONE SEBASTIAN T

IPC: H04L12/50

CPC classification number: H04L49/15 ,  H04L49/109 ,  H04L49/252

Abstract: A method and apparatus for providing communication between various cores (1-5) located in an integrated circuit. The method and apparatus uses Hubs/Routers (6-10) to facilitate and manage communication of data from /between the cores (1-5) according to a specified methodology.

Abstract translation: 一种用于在位于集成电路中的各种核心（1-5）之间提供通信的方法和装置。 该方法和装置使用集线器/路由器（6-10）根据指定的方法来促进和管理/内核（1-5）之间的数据通信。

公开(公告)号：WO2005008732A3

公开(公告)日：2007-07-05

申请号：PCT/US2004022267

申请日：2004-07-09

Applicant: IBM ,  BLANCO RAFAEL ,  COHN JOHN M ,  GOODNOW KENNETH J ,  STOUT DOUGLAS W ,  VENTRONE SEBASTIAN T

Inventor： BLANCO RAFAEL ,  COHN JOHN M ,  GOODNOW KENNETH J ,  STOUT DOUGLAS W ,  VENTRONE SEBASTIAN T

IPC: G11C16/04 ,  G11C19/08 ,  H01L20060101

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y02D10/171

Abstract: A structure for processing data on a semiconductor device comprising an input island (14), a processing island (8), and an output island (12) formed on the semiconductor device (18). The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.

Abstract translation: 一种用于在半导体器件上处理数据的结构，包括形成在半导体器件（18）上的输入岛（14），处理岛（8）和输出岛（12）。 输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。 处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。 输出岛适于由第二规定电压供电。 处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。 第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。

公开(公告)号：WO2005006453A8

公开(公告)日：2007-03-15

申请号：PCT/US2004021244

申请日：2004-07-01

Applicant: IBM ,  HORTON ROBERT S ,  MILTON DAVID W ,  OGILVIE CLARENCE R ,  SCHANELY PAUL M ,  VENTRONE SEBASTIAN T

Inventor： HORTON ROBERT S ,  MILTON DAVID W ,  OGILVIE CLARENCE R ,  SCHANELY PAUL M ,  VENTRONE SEBASTIAN T

IPC: H01L31/107 ,  G06F13/42 ,  H04L25/14

CPC classification number: G06F13/4247 ,  H04L25/14

Abstract: The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment (120) of a segmented data line (120-122) and then propagating the first data portion along a second segment (121) of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line. The invention breaks a single data transmission into such different data portions and later reassembles the different data portions back into the single data transmission after all of the different data portions have been individually transmitted along all portions of the segmented data line.

Abstract translation: 本发明通过首先沿着分段数据线（120-122）的第一段（120）传播第一数据部分，然后沿着分段数据线（120-122）的第二段（121）传播第一数据部分，在集成电路芯片上传输数据 数据线并沿着分段数据线的第一段同时传播第二数据部分。 本发明将单个数据传输划分成这样的不同数据部分，并且在所有不同的数据部分已经沿着分段数据线的所有部分单独发送之后，将不同的数据部分重新组合成单​​个数据传输。