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公开(公告)号：DE69112145T2
公开(公告)日：1996-05-02
申请号：DE69112145
申请日：1991-06-27
Applicant: IBM
Inventor： DIMMICK ROGER FRANCIS , KLEVE VERNON JOHN , MEYER TIMOTHY LOUIS , THOMPSON GARY ALLEN , WESTPHAL GORDON WILBUR
Abstract: An enclosure for different subsystem variations of a data processing system has a box with front and rear regions separated by an interconnection carrier. The front is divided into standard-size bays for functional modules, while support modules slide into rear bays. A vertical central carrier contains electrical interconnections between the functional and support modules. An environmental module provides cooling air through the enclosure.
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公开(公告)号：DE68915835D1
公开(公告)日：1994-07-14
申请号：DE68915835
申请日：1989-01-31
Applicant: IBM
Inventor： CASANOVA WAYNE JOSEPH , DIMMICK ROGER FRANCIS , HALL WILLIAM ALLEN , HOMAN LESTER CHARLES , LUKES FRANK JOHN , MARTIN BRADLEY LEWIS , MOSLEY CLAUDE JOSEPH , RECKINGER ARTHUR PIERRE , SCHAEFER PAUL WILLIAM , SQUILLACE ZANTI DAVID , WESTPHAL GORDON WILBUR , WHEELER STEPHEN EDWARD
Abstract: A data processing system is shown packaged in an enclosure wherein the system frame or chassis and a cable carrier are separately fabricated and thereafter merged to provide an enclosure (11) with open ends and a central cable carrier (20) that mounts connections for the system components. The system components (22, 23) are slideably received by the enclosure and are self docking as the electrical connections with the system power and signal lines are completed as the components arrive at the fully inserted, latched position. Keying means are also provided to require the user to install the components at both the correct location and with the correct orientation.
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公开(公告)号：DE69022018D1
公开(公告)日：1995-10-05
申请号：DE69022018
申请日：1990-11-27
Applicant: IBM
Inventor： CASANOVA WAYNE JOSEPH , CORFITS WILLIAM DALE , DIMMICK ROGER FRANCIS , THOMPSON GARY ALLEN , THORPE JAMES ROBERT , WHEELER STEPHEN EDWARD
Abstract: A double-sided central electronics complex (CEC) (20) is provided for increasing the logic card density in a logic cage or CEC. Specifically, two logic cages or sub-enclosures (22, 24) are integrated, sharing one backplane card so that logic elements may be plugged into the CEC from both sides. The CEC is formed by unitary sheet metal side plates, top and bottom cast or guides (26, 28) and a single double-sided backplane assembly (38).
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公开(公告)号：DE2536508A1
公开(公告)日：1976-06-24
申请号：DE2536508
申请日：1975-08-16
Applicant: IBM
Inventor： CHECK GLEN PETER , DIMMICK ROGER FRANCIS
Abstract: A counter circuit counts all transitions of two or more overlapped out of phase bi-level signals under control of a start signal by combining the input signals via an exclusive OR circuit into a single signal having the transitions of all input signals. The levels of this single signal are applied to a polarity hold circuit and the level present upon the occurrence of an asynchronously occurring start signal is stored therein. The polarity hold circuit provides a pair of gating signals to a logical AND/OR network having an output containing both the positive and negative transitions of the single signal. The detected transitions are fed into a binary counter whose first stage consists of the AND/OR network.
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公开(公告)号：DE69022018T2
公开(公告)日：1996-04-18
申请号：DE69022018
申请日：1990-11-27
Applicant: IBM
Inventor： CASANOVA WAYNE JOSEPH , CORFITS WILLIAM DALE , DIMMICK ROGER FRANCIS , THOMPSON GARY ALLEN , THORPE JAMES ROBERT , WHEELER STEPHEN EDWARD
Abstract: A double-sided central electronics complex (CEC) (20) is provided for increasing the logic card density in a logic cage or CEC. Specifically, two logic cages or sub-enclosures (22, 24) are integrated, sharing one backplane card so that logic elements may be plugged into the CEC from both sides. The CEC is formed by unitary sheet metal side plates, top and bottom cast or guides (26, 28) and a single double-sided backplane assembly (38).
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Patent Agency Ranking
公开(公告)号：DE69010655T2
公开(公告)日：1995-01-12
申请号：DE69010655
申请日：1990-11-27
Applicant: IBM
Inventor： AUG CONRAD JEAN , CASANOVA WAYNE JOSEPH , CORFITS WILLIAM DALE , DIMMICK ROGER FRANCIS , WHEELER STEPHEN EDWARD
Abstract: A double-sided backplane assembly (20) is provided for increasing the logic element density in a logic cage or CEC. The backplane assembly is multi-layered with a backplane card (22) centrally located between a stiffener (30) and an EMC shield (36) affixed to each side thereof. Connectors for connecting logic elements to the backplane card are provided on both sides of the backplane card, so that a logic cage having two sub-cages may be provided, the two sub-cages sharing the one backplane assembly.
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公开(公告)号：DE68915835T2
公开(公告)日：1994-12-08
申请号：DE68915835
申请日：1989-01-31
Applicant: IBM
Inventor： CASANOVA WAYNE JOSEPH , DIMMICK ROGER FRANCIS , HALL WILLIAM ALLEN , HOMAN LESTER CHARLES , LUKES FRANK JOHN , MARTIN BRADLEY LEWIS , MOSLEY CLAUDE JOSEPH , RECKINGER ARTHUR PIERRE , SCHAEFER PAUL WILLIAM , SQUILLACE ZANTI DAVID , WESTPHAL GORDON WILBUR , WHEELER STEPHEN EDWARD
Abstract: A data processing system is shown packaged in an enclosure wherein the system frame or chassis and a cable carrier are separately fabricated and thereafter merged to provide an enclosure (11) with open ends and a central cable carrier (20) that mounts connections for the system components. The system components (22, 23) are slideably received by the enclosure and are self docking as the electrical connections with the system power and signal lines are completed as the components arrive at the fully inserted, latched position. Keying means are also provided to require the user to install the components at both the correct location and with the correct orientation.
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公开(公告)号：DE69112145D1
公开(公告)日：1995-09-21
申请号：DE69112145
申请日：1991-06-27
Applicant: IBM
Inventor： DIMMICK ROGER FRANCIS , KLEVE VERNON JOHN , MEYER TIMOTHY LOUIS , THOMPSON GARY ALLEN , WESTPHAL GORDON WILBUR
Abstract: An enclosure for different subsystem variations of a data processing system has a box with front and rear regions separated by an interconnection carrier. The front is divided into standard-size bays for functional modules, while support modules slide into rear bays. A vertical central carrier contains electrical interconnections between the functional and support modules. An environmental module provides cooling air through the enclosure.
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公开(公告)号：DE69010655D1
公开(公告)日：1994-08-18
申请号：DE69010655
申请日：1990-11-27
Applicant: IBM
Inventor： AUG CONRAD JEAN , CASANOVA WAYNE JOSEPH , CORFITS WILLIAM DALE , DIMMICK ROGER FRANCIS , WHEELER STEPHEN EDWARD
Abstract: A double-sided backplane assembly (20) is provided for increasing the logic element density in a logic cage or CEC. The backplane assembly is multi-layered with a backplane card (22) centrally located between a stiffener (30) and an EMC shield (36) affixed to each side thereof. Connectors for connecting logic elements to the backplane card are provided on both sides of the backplane card, so that a logic cage having two sub-cages may be provided, the two sub-cages sharing the one backplane assembly.
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公开(公告)号：DE2312043A1
公开(公告)日：1973-10-18
申请号：DE2312043
申请日：1973-03-10
Applicant: IBM
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