ON-CHIP INTEGRATED VOLTAGE-CONTROLLED VARIABLE INDUCTOR

    公开(公告)号:EP2243162A4

    公开(公告)日:2017-11-01

    申请号:EP09705653

    申请日:2009-01-28

    Applicant: IBM

    CPC classification number: H01F21/005 H01F17/0006 H01F21/12 Y10T29/4902

    Abstract: On-chip integrated variable inductors, methods of making and tuning an on-chip integrated variable inductor, and design structures embodying a circuit containing the on-chip integrated variable inductor. The inductor generally includes a signal line configured to carry an electrical signal, a ground line positioned in proximity to the signal line, and at least one control unit electrically coupled with the ground line. The at least one control unit is configured to open and close switch a current path connecting the ground line with a ground potential so as to change an inductance of the signal line.

    On-chip inductor with magnetic core
    4.
    发明专利
    On-chip inductor with magnetic core 有权
    带磁芯的片上电感器

    公开(公告)号:JP2006013111A

    公开(公告)日:2006-01-12

    申请号:JP2004187571

    申请日:2004-06-25

    Abstract: PROBLEM TO BE SOLVED: To provide an inductor being formed on an integrated circuit chip.
    SOLUTION: The on-chip inductor comprises one or a plurality of inner layers (12) existing between two or more outer layers (14), an inductor metal wiring turn (16) included in the one or a plurality of inner layers (12), and a magnetic member for forming the two or more outer layers (14) and the one or a plurality of inner layers (12). In one embodiment, the magnetic member is photoresist paste containing magnetic particles. In another embodiment, the magnetic member is a series of magnetic metal strips (32 and 36) arranged, respectively, on the first and second parts (30 and 34) of the two or more outer layers (14) and on the one or a plurality of inner layers (12), respectively. The series of magnetic metal strips on the first and second parts (30 and 34) form a lattice pattern. Other mode includes deposition of a compound controlled adjustably and a control winding having an adjustable current.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题:提供形成在集成电路芯片上的电感器。 片上电感器包括存在于两个或多个外层(14)之间的一个或多个内层(12),包含在一个或多个内层(14)中的电感器金属布线匝(16) (12),以及用于形成所述两个或更多个外层(14)和所述一个或多个内层(12)的磁性构件。 在一个实施例中,磁性构件是含有磁性颗粒的光致抗蚀剂浆料。 在另一个实施例中,磁性构件是分别布置在两个或多个外层(14)的第一和第二部分(30和34)上并且在一个或多个外层(14)上的一系列磁性金属条(32和36) 多个内层(12)。 第一和第二部分(30和34)上的一系列磁性金属条形成格子图案。 其他模式包括可调整控制的化合物的沉积和具有可调电流的控制绕组。 版权所有(C)2006,JPO&NCIPI

    METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER
    5.
    发明申请
    METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER 审中-公开
    通硅威威尔金森功分器的方法,结构和设计结构

    公开(公告)号:WO2011028385A3

    公开(公告)日:2011-06-23

    申请号:PCT/US2010045249

    申请日:2010-08-12

    Abstract: A method, structure, and design structure for a through-silicon- via Wilkinson power divider (100). A method includes: forming an input (105) on a first side of a substrate(200); forming a first leg (110a) comprising a first through-silicon- via (120a) formed in the substrate, wherein the first leg electrically connects the input and a first output (115a); forming a second leg (110b) comprising a second through-silicon- via (120b) formed in the substrate, wherein the second leg electrically connects the input and a second output (115b), and forming a resistor (125) electrically connected between the first output and the second output.

    Abstract translation: 通过威尔金森功率分配器(100)的硅通孔的方法,结构和设计结构。 一种方法包括:在衬底(200)的第一侧上形成输入(105); 形成包括形成在所述衬底中的第一硅通孔(120a)的第一腿(110a),其中所述第一腿电连接所述输入和第一输出(115a); 形成包括形成在所述衬底中的第二硅通孔(120b)的第二腿(110b),其中所述第二腿电连接所述输入和第二输出(115b),并且形成电连接在所述第一硅通孔 第一个输出和第二个输出。

    ESTRUCTURA DE DISEÑO, ESTRUCTURA Y METODO PARA PROPORCIONAR UNA LINEA DE TRANSMISION CON RETARDO VARIABLE EN LA MICROPLAQUETA CON IMPEDANCIA CARACTERISTICA FIJA.

    公开(公告)号:MX2010013267A

    公开(公告)日:2011-02-25

    申请号:MX2010013267

    申请日:2009-06-17

    Applicant: IBM

    Abstract: Una estructura de diseño, una estructura y un método para proporcionar una línea de transmisión con retardo variable en la microplaqueta con una impedancia característica fija. Una estructura de la línea de transmisión incluye una línea de la señal (50) (por ejemplo, S), una primera estructura de retorno a tierra (55) (por ejemplo, G1), que causa un primer retardo (ti) y una primera impedancia característica (Zo1) en la estructura de la línea de transmisión, y una segunda estructura de retorno a tierra (75) (por ejemplo, G2), que causa un segundo retardo (t2) y una segunda impedancia característica (Zo2) en la estructura de la línea de transmisión. El primer retardo (t1) es diferente del segundo retardo (t2), y la primera impedancia característica (Zo1) es sustancialmente la misma que la segunda impedancia característica (Zo2).

    Verfahren, Struktur und Entwurfsstruktur für einen Wilkinson-Leistungsteiler mit Durchkontaktierung durch Silicium

    公开(公告)号:DE112010003420T5

    公开(公告)日:2012-09-20

    申请号:DE112010003420

    申请日:2010-08-12

    Applicant: IBM

    Abstract: Verfahren, Struktur und Entwurfsstruktur für einen Wilkinson-Leistungsteiler (100) mit Durchkontaktierung durch Silicium. Das Verfahren umfasst das Folgende: Bilden eines Eingangs (105) auf einer ersten Seite eines Substrats (200); Bilden eines ersten Ausläufers (110a), der eine erste in dem Substrat ausgebildete Durchkontaktierung durch Silicium (120a) umfasst, wobei der erste Ausläufer den Eingang und einen ersten Ausgang (115a) elektrisch verbindet; Bilden eines zweiten Ausläufers (110b), welcher eine zweite in dem Substrat ausgebildete Durchkontaktierung durch Silicium (120b) umfasst, wobei der zweite Ausläufer den Eingang und einen zweiten Ausgang (115b) elektrisch verbindet; und Bilden eines Widerstands (125), der elektrisch zwischen den ersten Ausgang und den zweiten Ausgang geschaltet ist.

    ON-CHIP MILLIMETER WAVE LANGE COUPLER

    公开(公告)号:CA2750412A1

    公开(公告)日:2010-09-23

    申请号:CA2750412

    申请日:2010-02-25

    Applicant: IBM

    Abstract: A Lange coupler having a first plurality of lines (210, 220) on a first level and a second plurality of lines (230, 240) on a second level. At least one line on the first level is cross-coupled to a respective line on the second level via electromagnetic waves (250, 260, 270, 280) traveling through the first and second plurality of lines. The first and second plurality of lines may be made of metal, and the first level may be higher than the second level. A substrate (200) may be provided into which the first and second plurality of lines are etched so as to define an on-chip Lange coupler.

    METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER

    公开(公告)号:GB2485718A

    公开(公告)日:2012-05-23

    申请号:GB201203499

    申请日:2010-08-12

    Applicant: IBM

    Abstract: A method, structure, and design structure for a through-silicon- via Wilkinson power divider (100). A method includes: forming an input (105) on a first side of a substrate(200); forming a first leg (110a) comprising a first through-silicon- via (120a) formed in the substrate, wherein the first leg electrically connects the input and a first output (115a); forming a second leg (110b) comprising a second through-silicon- via (120b) formed in the substrate, wherein the second leg electrically connects the input and a second output (115b), and forming a resistor (125) electrically connected between the first output and the second output.

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