公开(公告)号：EP1782473A4

公开(公告)日：2010-03-17

申请号：EP05757090

申请日：2005-06-06

Applicant: IBM

Inventor： STEIGERWALT MICHAEL ,  KUMAR MAHENDER ,  HO HERBERT L ,  DOBUZINSKY DAVID ,  FALTERMEIER JOHNATHAN

IPC: H01L27/12 ,  H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

Abstract: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

公开(公告)号：WO2006009613A2

公开(公告)日：2006-01-26

申请号：PCT/US2005019815

申请日：2005-06-06

Applicant: IBM ,  STEIGERWALT MICHAEL ,  KUMAR MAHENDER ,  HO HERBERT L ,  DOBUZINSKY DAVID ,  FALTERMEIER JOHNATHAN

Inventor： STEIGERWALT MICHAEL ,  KUMAR MAHENDER ,  HO HERBERT L ,  DOBUZINSKY DAVID ,  FALTERMEIER JOHNATHAN

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/316 ,  H01L21/762

CPC classification number: H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

Abstract: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

Abstract translation: 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，在SOI和体硅区域中同时蚀刻STI，进行蚀刻到体硅区域中期望的深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

公开(公告)号：DE10352070A1

公开(公告)日：2004-05-27

申请号：DE10352070

申请日：2003-11-07

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DOBUZINSKY DAVID ,  PANDA SIDDHARTHA ,  WEIS ROLF ,  WISE RICHARD

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/461 ,  H01L21/68 ,  H01L21/8242

Abstract: A method is disclosed for improving etch uniformity in deep silicon etching of a monocrystalline silicon wafer. Such method includes forming a pad dielectric layer on a wafer including monocrystalline silicon, forming a silicon layer over the pad dielectric layer, and then applying a clamp to an edge of the wafer. The silicon layer is then removed except in areas protected by the clamp. Thereafter, a hardmask layer is applied and patterned on the wafer; and the wafer is then directionally etched with the patterned hardmask to etch trenches in the monocrystalline silicon.In such manner, a source of silicon (in the silicon layer) is provided at the wafer edge, such that the silicon loading is improved. In addition, the silicon layer at the wafer edge forms a blocking layer which prevents formation of black silicon.