公开(公告)号：EP1782473A4

公开(公告)日：2010-03-17

申请号：EP05757090

申请日：2005-06-06

Applicant: IBM

Inventor： STEIGERWALT MICHAEL ,  KUMAR MAHENDER ,  HO HERBERT L ,  DOBUZINSKY DAVID ,  FALTERMEIER JOHNATHAN

IPC: H01L27/12 ,  H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

Abstract: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

公开(公告)号：WO0245131A3

公开(公告)日：2003-05-15

申请号：PCT/US0144626

申请日：2001-11-28

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CHUDZIK MICHAEL ,  TEWS HELMUT ,  MCSTAY IRENE ,  KUDELKA STEPHAN ,  SETTLEMYER KENNETH ,  JAMMY RAJARAO ,  FALTERMEIER JOHNATHAN

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L27/1087 ,  H01L28/84 ,  Y10S438/964

Abstract: Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer (43) on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps (44) therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves (46) on the walls of the trench region.

Abstract translation: 提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。 一种方法包括以下步骤：在下沟槽区域的暴露壁上形成不连续的多晶硅层（43），所述不连续的多晶硅层在其中具有暴露所述衬底部分的间隙（44） 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽（46）。

公开(公告)号：WO2006009613A2

公开(公告)日：2006-01-26

申请号：PCT/US2005019815

申请日：2005-06-06

Applicant: IBM ,  STEIGERWALT MICHAEL ,  KUMAR MAHENDER ,  HO HERBERT L ,  DOBUZINSKY DAVID ,  FALTERMEIER JOHNATHAN

Inventor： STEIGERWALT MICHAEL ,  KUMAR MAHENDER ,  HO HERBERT L ,  DOBUZINSKY DAVID ,  FALTERMEIER JOHNATHAN

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/316 ,  H01L21/762

CPC classification number: H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

Abstract: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

Abstract translation: 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，在SOI和体硅区域中同时蚀刻STI，进行蚀刻到体硅区域中期望的深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

公开(公告)号：DE10331195B4

公开(公告)日：2006-12-28

申请号：DE10331195

申请日：2003-07-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DOBUZINSKY DAVID M ,  FALTERMEIER JOHNATHAN ,  FLAITZ PHILIP ,  IWATAKE MICHAEL M ,  MALDEI MICHAEL ,  NINOMIYA LISA Y ,  RAMACHARDRAN RAVIKUMAR ,  SARDESAI VIRAI Y ,  SNAVELY COLLEEN M ,  WANG YUN YU

IPC: H01L21/8242 ,  H01L21/20 ,  H01L21/285 ,  H01L21/306

Abstract: In a method of preparing a DRAM wherein doped poly-Si is used as a CB contact as well as a source of doping in the contact region, and where in amorphous Si is used to fill the CB contact, the improvement of enhancing epitaxial regrowth in amorphous Poly CB contacts, comprising: a) affecting a CB liner reactive ion etch on a substrate to remove SiN and SiO; b) affecting an O plasma clean (in-situ or ex-situ); c) affecting a Huang AB clean; d) affecting a dilute hydrofluoric acid (DHF) clean; e) depositing amorphous Si; and f) annealing to recrystallize and regrow amorphous CB.

公开(公告)号：DE10331195A1

公开(公告)日：2004-02-12

申请号：DE10331195

申请日：2003-07-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DOBUZINSKY DAVID M ,  FALTERMEIER JOHNATHAN ,  FLAITZ PHILIP ,  IWATAKE MICHAEL M ,  MALDEI MICHAEL ,  NINOMIYA LISA Y ,  RAMACHARDRAN RAVIKUMAR ,  SARDESAI VIRAI Y ,  SNAVELY COLLEEN M ,  WANG YUN YU

IPC: H01L21/20 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8242

Abstract: In a method of preparing a DRAM wherein doped poly-Si is used as a CB contact as well as a source of doping in the contact region, and where in amorphous Si is used to fill the CB contact, the improvement of enhancing epitaxial regrowth in amorphous Poly CB contacts, comprising: a) affecting a CB liner reactive ion etch on a substrate to remove SiN and SiO; b) affecting an O plasma clean (in-situ or ex-situ); c) affecting a Huang AB clean; d) affecting a dilute hydrofluoric acid (DHF) clean; e) depositing amorphous Si; and f) annealing to recrystallize and regrow amorphous CB.