公开(公告)号：EP0814507A1

公开(公告)日：1997-12-29

申请号：EP97304339

申请日：1997-06-20

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  POSCHENRIEDER BERNHARD ,  SHORT ALVIN P ,  SRINIVASAN RADHIKA ,  STENGL REINHARD J ,  HO HERBERT L

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: Method for forming three-dimensional device structures such as a trench capacitor DRAM cell comprising a second device (370) formed over a first device (315) is disclosed. A layer (350,355) having a single crystalline top surface (350) is formed above the first device (315) to provide the base for forming the active area of the second device.

Abstract translation: 公开了一种用于形成三维器件结构的方法，例如包括形成在第一器件（315）上的第二器件（370）的沟槽电容器DRAM单元。 具有单晶顶表面（350）的层（350,355）形成在第一装置（315）上方，以提供用于形成第二装置的有效区域的基座。

公开(公告)号：EP1782473A4

公开(公告)日：2010-03-17

申请号：EP05757090

申请日：2005-06-06

Applicant: IBM

Inventor： STEIGERWALT MICHAEL ,  KUMAR MAHENDER ,  HO HERBERT L ,  DOBUZINSKY DAVID ,  FALTERMEIER JOHNATHAN

IPC: H01L27/12 ,  H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

Abstract: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

公开(公告)号：EP2286444A4

公开(公告)日：2012-11-21

申请号：EP09747138

申请日：2009-04-28

Applicant: IBM

Inventor： ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

IPC: H01L23/525 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1397830A4

公开(公告)日：2009-03-11

申请号：EP01988335

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer (42) of Ti, followed by a conformal liner layer (46) of CVD TiN, followed in turn by a final liner layer (48) of TA or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the copper to an acceptable amount.

Abstract translation: 在具有铜互连和低k层间电介质的集成电路中，发现热处理后开路的问题，并通过使用Ti的第一衬垫层（42），随后使用CVD共形衬垫层（46） TiN，然后依次是TA或TaN的最终衬垫层（48），因此改善了通孔和下面的铜层之间的粘合性，同时将由Ti和铜之间的合金化引起的电阻的增加减少到可接受的量。

公开(公告)号：EP0794567A3

公开(公告)日：2000-01-12

申请号：EP97102901

申请日：1997-02-21

Applicant: SIEMENS AG ,  IBM

Inventor： HO HERBERT L ,  SRINIVASAN RADHIKA ,  HALLE SCOTT D ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  MANDELMAN JACK A ,  JASO MARK ANTHONY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10861 ,  H01L21/76232 ,  H01L27/10832 ,  H01L28/82 ,  Y10S438/973

Abstract: A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.

公开(公告)号：JP2005244224A

公开(公告)日：2005-09-08

申请号：JP2005044980

申请日：2005-02-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HO HERBERT L ,  KUMAR MAHENDER ,  OUYANG QIQING ,  PAPWORTH PAUL A ,  SHERAW CHRISTOPHER D ,  STEIGERWALT MICHAEL D

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H01L27/082 ,  H01L27/12 ,  H01L29/73 ,  H01L29/732

CPC classification number: H01L29/7317

Abstract: PROBLEM TO BE SOLVED: To provide a "non-collector" silicon-on-insulator (SOI) bipolar junction transistor not provided with an impurity doped collector.
SOLUTION: The bipolar transistor comprises a conductive backside electrode that receives an applied bias voltage, an insulating layer located on the conductive backside electrode, and an extrinsic collector containing a base containing a first conductivity type dopant and a second conductivity type dopant adjacent to the base and further comprises an emitter provided with a semiconductor layer located on the insulating layer and a second semiconductor layer located on a part of the base and containing the second conductivity type dopant. The conductive backside electrode is biased to form an inverted potential layer at an interface between the first semiconductor layer and the insulating layer in the base.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供未设置杂质掺杂集电极的“非集电极”绝缘体上硅（SOI）双极结型晶体管。 解决方案：双极晶体管包括接收施加的偏置电压的导电背面电极，位于导电背面电极上的绝缘层，以及包含含有第一导电类型掺杂剂和第二导电类型掺杂剂的基底的非本征集电极 并且还包括设置有位于所述绝缘层上的半导体层的发射体和位于所述基底的一部分上并且包含所述第二导电型掺杂剂的第二半导体层。 导电背面电极被偏置以在基底中的第一半导体层和绝缘层之间的界面处形成反向电位层。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2006253684A

公开(公告)日：2006-09-21

申请号：JP2006061418

申请日：2006-03-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  RAMACHANDRA DEIBAKARUNI ,  HO HERBERT L ,  KARL J REEDENSU

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/08 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: PROBLEM TO BE SOLVED: To provides a structure including a trench capacitor array at least part of which is arranged under an embedded oxide layer of an SOI substrate.
SOLUTION: Each trench capacitor shares a common unitary embedded capacitor plate including at least part of a first unitary semiconductor region arranged under an embedded oxide layer. An upper boundary of the embedded capacitor plate defines a plane extending laterally over the whole trench capacitor array parallel to the major surface of a substrate. In a particular embodiment starting at an SOI substrate or a bulk substrate, the trench array and contact holes are formed at the same time such that the contact holes extend in the same depth as that of the trenches. Preferably, the width of the contact hole is substantially large compared with that of the trench, thereby forming conductive contact vias at the same time by processing used for forming a trench capacitor extending along the wall of the trench.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种包括沟槽电容器阵列的结构，其至少一部分布置在SOI衬底的嵌入式氧化物层的下方。 解决方案：每个沟槽电容器共享共同的单一嵌入式电容器板，其包括布置在嵌入式氧化物层下方的第一单元半导体区域的至少一部分。 嵌入式电容器板的上边界限定了平行于衬底的主表面的整个沟槽电容器阵列上横向延伸的平面。 在从SOI衬底或体衬底开始的特定实施例中，沟槽阵列和接触孔同时形成，使得接触孔在与沟槽的深度相同的深度上延伸。 优选地，接触孔的宽度与沟槽的宽度相比基本上大，由此通过用于形成沿沟槽壁延伸的沟槽电容器的处理同时形成导电接触孔。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO02056342A3

公开(公告)日：2004-01-08

申请号：PCT/US0149138

申请日：2001-12-19

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BOETTCHER STEVEN H ,  HO HERBERT L ,  HOINKIS MARK ,  LEE HYUN KOO ,  WANG YUN-YU ,  WONG KWONG HON

IPC: C23C16/34 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer (42) of Ti, followed by a conformal liner layer (46) of CVD TiN, followed in turn by a final liner layer (48) of TA or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the copper to an acceptable amount.

Abstract translation: 在具有铜互连和低k层间电介质的集成电路中，通过使用Ti的第一衬垫层（42），然后使用CVD的保形衬垫层（46），发现并解决了热处理后的开路问题 TiN，然后是TA或TaN的最终衬垫层（48），从而改善通孔和下面的铜层之间的粘附性，同时将由Ti和铜之间的合金化引起的电阻增加减少到可接受的量。

公开(公告)号：WO2009140052A3

公开(公告)日：2010-01-21

申请号：PCT/US2009041861

申请日：2009-04-28

Applicant: IBM ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

Inventor： ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

IPC: H01L21/335

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Abstract translation: 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。

公开(公告)号：WO2006009613A2

公开(公告)日：2006-01-26

申请号：PCT/US2005019815

申请日：2005-06-06

Applicant: IBM ,  STEIGERWALT MICHAEL ,  KUMAR MAHENDER ,  HO HERBERT L ,  DOBUZINSKY DAVID ,  FALTERMEIER JOHNATHAN

Inventor： STEIGERWALT MICHAEL ,  KUMAR MAHENDER ,  HO HERBERT L ,  DOBUZINSKY DAVID ,  FALTERMEIER JOHNATHAN

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/316 ,  H01L21/762

CPC classification number: H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

Abstract: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

Abstract translation: 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，在SOI和体硅区域中同时蚀刻STI，进行蚀刻到体硅区域中期望的深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。