公开(公告)号：EP1911088A4

公开(公告)日：2008-11-12

申请号：EP06789024

申请日：2006-08-01

Applicant: IBM

Inventor： NAYFEH HASAN M ,  KUMAR MAHENDER ,  FANG SUNFEI ,  KEDZIERSKI JAKUB T ,  CABRAL CYRIL JR

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L29/00

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer (56) that is thick enough to fully convert the semiconductor layer (22) to a semiconductor metal alloy in a first MOSFET type region (40) but only thick enough to partially convert the semiconductor layer (20) to a semiconductor metal alloy in a second MOSFET type region (30). In one embodiment, the gate stack in a first MOSFET region (40) is recessed prior to forming the metal-containing layer (56) so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer (56) is thinned over a first type MOSFET region (40) relative to a second type MOSFET region (30) prior to the conversion process.

Abstract translation: 描述了MOSFET结构和形成方法。 该方法包括形成厚度足以在第一MOSFET型区域（40）中将半导体层（22）完全转换成半导体金属合金的含金属层（56），但其厚度仅足以部分地将半导体层（ 20）连接到第二MOSFET型区域（30）中的半导体金属合金。 在一个实施例中，在形成含金属层（56）之前使第一MOSFET区域（40）中的栅极堆叠凹陷，使得第一MOSFET半导体堆叠的高度小于第二MOSFET半导体堆叠的高度。 在另一个实施例中，在转换过程之前，含金属层（56）在第一类型MOSFET区域（40）上相对于第二类型MOSFET区域（30）变薄。

公开(公告)号：EP1782473A4

公开(公告)日：2010-03-17

申请号：EP05757090

申请日：2005-06-06

Applicant: IBM

Inventor： STEIGERWALT MICHAEL ,  KUMAR MAHENDER ,  HO HERBERT L ,  DOBUZINSKY DAVID ,  FALTERMEIER JOHNATHAN

IPC: H01L27/12 ,  H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

Abstract: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

公开(公告)号：JP2005244224A

公开(公告)日：2005-09-08

申请号：JP2005044980

申请日：2005-02-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HO HERBERT L ,  KUMAR MAHENDER ,  OUYANG QIQING ,  PAPWORTH PAUL A ,  SHERAW CHRISTOPHER D ,  STEIGERWALT MICHAEL D

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H01L27/082 ,  H01L27/12 ,  H01L29/73 ,  H01L29/732

CPC classification number: H01L29/7317

Abstract: PROBLEM TO BE SOLVED: To provide a "non-collector" silicon-on-insulator (SOI) bipolar junction transistor not provided with an impurity doped collector.
SOLUTION: The bipolar transistor comprises a conductive backside electrode that receives an applied bias voltage, an insulating layer located on the conductive backside electrode, and an extrinsic collector containing a base containing a first conductivity type dopant and a second conductivity type dopant adjacent to the base and further comprises an emitter provided with a semiconductor layer located on the insulating layer and a second semiconductor layer located on a part of the base and containing the second conductivity type dopant. The conductive backside electrode is biased to form an inverted potential layer at an interface between the first semiconductor layer and the insulating layer in the base.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供未设置杂质掺杂集电极的“非集电极”绝缘体上硅（SOI）双极结型晶体管。 解决方案：双极晶体管包括接收施加的偏置电压的导电背面电极，位于导电背面电极上的绝缘层，以及包含含有第一导电类型掺杂剂和第二导电类型掺杂剂的基底的非本征集电极 并且还包括设置有位于所述绝缘层上的半导体层的发射体和位于所述基底的一部分上并且包含所述第二导电型掺杂剂的第二半导体层。 导电背面电极被偏置以在基底中的第一半导体层和绝缘层之间的界面处形成反向电位层。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2007016514A3

公开(公告)日：2007-04-05

申请号：PCT/US2006029800

申请日：2006-08-01

Applicant: IBM ,  NAYFEH HASAN M ,  KUMAR MAHENDER ,  FANG SUNFEI ,  KEDZIERSKI JAKUB T ,  CABRAL CYRIL JR

Inventor： NAYFEH HASAN M ,  KUMAR MAHENDER ,  FANG SUNFEI ,  KEDZIERSKI JAKUB T ,  CABRAL CYRIL JR

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L29/00

CPC classification number: H01L21/823835 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer (56) that is thick enough to fully convert the semiconductor layer (22) to a semiconductor metal alloy in a first MOSFET type region (40) but only thick enough to partially convert the semiconductor layer (20) to a semiconductor metal alloy in a second MOSFET type region (30). In one embodiment, the gate stack in a first MOSFET region (40) is recessed prior to forming the metal-containing layer (56) so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer (56) is thinned over a first type MOSFET region (40) relative to a second type MOSFET region (30) prior to the conversion process.

Abstract translation: 描述了MOSFET结构和形成方法。 该方法包括形成足够厚的含金属层（56），以将半导体层（22）完全转换为第一MOSFET型区域（40）中的半导体金属合金，但仅足够厚以部分地转换半导体层（ 20）连接到第二MOSFET型区域（30）中的半导体金属合金。 在一个实施例中，在形成含金属层（56）之前，第一MOSFET区域（40）中的栅极堆叠是凹进的，使得第一MOSFET半导体堆叠的高度小于第二MOSFET半导体堆叠的高度。 在另一个实施例中，在转换过程之前，相对于第二类型MOSFET区域（30），含金属层（56）在第一类型MOSFET区域（40）上变薄。

公开(公告)号：WO2006009613A2

公开(公告)日：2006-01-26

申请号：PCT/US2005019815

申请日：2005-06-06

Applicant: IBM ,  STEIGERWALT MICHAEL ,  KUMAR MAHENDER ,  HO HERBERT L ,  DOBUZINSKY DAVID ,  FALTERMEIER JOHNATHAN

Inventor： STEIGERWALT MICHAEL ,  KUMAR MAHENDER ,  HO HERBERT L ,  DOBUZINSKY DAVID ,  FALTERMEIER JOHNATHAN

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/316 ,  H01L21/762

CPC classification number: H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

Abstract: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

Abstract translation: 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，在SOI和体硅区域中同时蚀刻STI，进行蚀刻到体硅区域中期望的深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。