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公开(公告)号：JP2004192621A
公开(公告)日：2004-07-08
申请号：JP2003390006
申请日：2003-11-19
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation IPC: G06F15/17 , G06F12/02 , G06F15/16 , G06F15/167 , G06F15/173 , H04L12/28 , H04L12/42 , H04L12/56 , H04L29/06 , H04L29/08
CPC classification number: H04L69/16 , G06F15/17 , H04L12/42 , H04L67/1002 , H04L69/161 , H04W28/14
Abstract: PROBLEM TO BE SOLVED: To provide an improved data processing system architecture reducing waiting time of communication between physically separating processors, reducing bus bandwidth consumption, and releasing the bus bandwidth for a general data transfer between the processor and a hierarchical memory system. SOLUTION: Information useful in pipelined multiprocessing or parallel multiprocessing is stored in each processor communication register (PCR). Each processor possesses an exclusive right to store a sector within each PCR and has continuous access to read the contents. Each processor cluster updates its exclusive sector within the PCRs, makes all other processors within the cluster network to be able to quickly see the change within the PCR data and bypasses a cache subsystem. COPYRIGHT: (C)2004,JPO&NCIPI
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公开(公告)号：JPH10301908A
公开(公告)日：1998-11-13
申请号：JP9777498
申请日：1998-04-09
Applicant: IBM
Inventor： ARIMILLI RAVI KUMAR , DODSON JOHN STEVEN , LEWIS JERRY DON , WILLIAMS DEREK EDWARD
IPC: G06F15/16 , G06F13/364 , G06F15/177
Abstract: PROBLEM TO BE SOLVED: To shorten waiting time by relating the weight of specified priority to respective plural requesters, allocating the highest present priority among plural present priorities to the priority before the plural requesters at random, and thereby approving the selected request. SOLUTION: A performance monitor 54 monitors and counts the requests or the like from the requesters 12-18. Then, at the time of receiving the requests more than the access to a shared resource 22 simultaneously approvable by a resource controller 20, the resource controller 20 relates the respective plural requesters to the respective weights of the plural priorities for indicating the possibility of allocating the highest present priority to the relating requester. Then, input from a pseudo random generator 24 is utilized, the highest priority is allocated to one of the requesters 12-18 by a practically non-critical method and the request of only the selected one of the requesters 12 18 is approved corresponding to the priority.
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公开(公告)号：JP2004326758A
公开(公告)日：2004-11-18
申请号：JP2004112533
申请日：2004-04-06
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： MCCALPIN JOHN DAVID , BARARAMU SHINHAROI , WILLIAMS DEREK EDWARD , KENNETH LEE WRIGHT
IPC: G06F9/30 , G06F9/45 , G06F12/08 , G06F15/177
CPC classification number: G06F9/30047 , G06F12/0804 , G06F12/0808 , G06F12/0837 , G06F12/0891
Abstract: PROBLEM TO BE SOLVED: To provide a local cache block flash command.
SOLUTION: A microprocessor and a related compiler support a local cache block flash command, where the execution unit of a processor determines an effective address. The processor makes a cache subsystem commit all pending references to the cache blocks, corresponding to the determined effective addresses. When a cache line referred to is corrected in a local cache (a cache subsystem, corresponding to the processor under execution of instructions), it is written back to a main memory. When the block referred to is valid in the local cache, although it is invalidated, but this is only the local cache. When the block referred to is not valid in the local cache, invalidation is not be carried out. A remote processor, which receives the local cache block flash instruction from the other processor through the system, ignores this command.
COPYRIGHT: (C)2005,JPO&NCIPI-
公开(公告)号：JP2004192620A
公开(公告)日：2004-07-08
申请号：JP2003389998
申请日：2003-11-19
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation IPC: G06F15/17 , G06F9/46 , G06F12/02 , G06F13/14 , G06F15/00 , G06F15/16 , G06F15/167 , G06F15/173 , G06F15/76
CPC classification number: G06F15/167
Abstract: PROBLEM TO BE SOLVED: To provide an improved data processing system architecture reducing waiting time of communication between physically separating processors, reducing bus bandwidth consumption, and releasing the bus bandwidth for a general data transfer between the processor and a hierarchical memory system. SOLUTION: The identical processing communication information useful in pipelined multiprocessing or parallel multiprocessing is stored in each processor communication register (PCR). Each processor possesses an exclusive right to store to a sector within each PCR and has continuous access to read PCR contents of itself. Each processor updates its exclusive sector within all of the PCRs using communication over a specialized bus, makes all other processors to be able to quickly see the change within the PCR data and bypasses a cache subsystem. COPYRIGHT: (C)2004,JPO&NCIPI
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公开(公告)号：JP2004192622A
公开(公告)日：2004-07-08
申请号：JP2003390008
申请日：2003-11-19
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation IPC: G06F15/17 , G06F9/46 , G06F12/02 , G06F15/167 , G06F15/173 , G06F15/76 , H04L12/28 , H04L12/56
CPC classification number: G06F15/173 , H04W28/14
Abstract: PROBLEM TO BE SOLVED: To provide an improved data processing system architecture reducing waiting time of communication between physically separating processors, reducing bus bandwidth consumption, and releasing the bus bandwidth for a general data transfer between the processor and a hierarchical memory system. SOLUTION: The identical processing communication information useful in pipelined multiprocessing or parallel multiprocessing is stored in each processor communication register (PCR). Each processor possesses an exclusive right to store to a sector within each PCR within a cluster network and has continuous access to read the PCR contents of itself. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, makes all other processors within the cluster network to be able to quickly see the change within the PCR data and bypasses a cache subsystem. COPYRIGHT: (C)2004,JPO&NCIPI
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Patent Agency Ranking
公开(公告)号：JP2004192619A
公开(公告)日：2004-07-08
申请号：JP2003389995
申请日：2003-11-19
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation IPC: G06F15/17 , G06F9/00 , G06F9/30 , G06F9/52 , G06F12/02 , G06F15/16 , G06F15/167 , G06F15/173
CPC classification number: G06F9/30101
Abstract: PROBLEM TO BE SOLVED: To provide an improved data processing system architecture reducing waiting time of communication between physically separating processors, reducing bus bandwidth consumption, and releasing the bus bandwidth for a general data transfer between the processor and a hierarchical memory system. SOLUTION: The identical processing communication information useful in pipelined multiprocessing or parallel multiprocessing is stored in each processor communication register (PCR). Each processor updates its exclusive sector within all of the PCRs, makes all other processors to be able to quickly see the change within the PCR data and bypasses a cache subsystem. BY temporarily restricting access to the information or by forcing all the processors to continuously compete and providing processor communication quickly transferred to all the processors, efficiency of the multiprocessor system can be improved. COPYRIGHT: (C)2004,JPO&NCIPI
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7.发明专利
公开(公告)号：GB2512804A
公开(公告)日：2014-10-08
申请号：GB201414384
申请日：2013-01-23
Applicant: IBM
Inventor： WILLIAMS DEREK EDWARD , GUTHRIE GUY LYNN , LE HIEN MINH , STUECHELI JEFFREY A
IPC: G06F12/08 , G06F15/167
Abstract: A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cachememory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.
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公开(公告)号：GB2502662B
公开(公告)日：2014-07-30
申请号：GB201303300
申请日：2013-02-25
Applicant: IBM
Inventor： GHAI SANJEEV , STARKE WILLIAM , GUTHRIE GUY LYNN , STUECHELI JEFFREY , WILLIAMS DEREK EDWARD , WILLIAMS PHILIP
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9.发明专利
公开(公告)号：GB2325764B
公开(公告)日：2001-12-12
申请号：GB9806536
申请日：1998-03-27
Applicant: IBM
Inventor： ARIMILLI RAVI KUMAR , DODSON JOHN STEVEN , LEWIS JERRY DON , WILLIAMS DEREK EDWARD
Abstract: Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces between controller logic and bus interface units within the controller. The generic interfaces are defined by extracting the essence of supported operations into a generic protocol. The interfaces themselves may be pulsed or held interfaces, depending on the character of the operation. Because the controller logic is isolated from the specific protocols required by a processor or bus architecture, the design may be directly transferred to new controllers for different protocols or processors by modifying the bus interface units appropriately.
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公开(公告)号：GB2325763A
公开(公告)日：1998-12-02
申请号：GB9806476
申请日：1998-03-27
Applicant: IBM
Inventor： ARIMILLI RAVI KUMAR , DODSON JOHN STEVEN , LEWIS JERRY DON , WILLIAMS DEREK EDWARD
Abstract: Cache and architectural-specific functions within a cache controller are layered (separated) to permit complex operations to be split into equivalent simple operations. Architectural variants of basic operations may thus be devolved, 310, into distinct cache and architectural operations and handled separately. The logic supporting the complex operations may thus be simplified and run faster. The functions are handled by respective controller units (212, 214, Fig 2).
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