公开(公告)号：DE3273531D1

公开(公告)日：1986-11-06

申请号：DE3273531

申请日：1982-06-02

Applicant: IBM

Inventor： DOUGHERTY WILLIAM E ,  FEINBERG IRVING ,  HUMENIK JAMES N ,  PLATT ALAN

IPC: H01L27/04 ,  H01G2/06 ,  H01G4/06 ,  H01G4/10 ,  H01G4/12 ,  H01G4/228 ,  H01G4/30 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01G1/14 ,  H01G1/035

Abstract: A decoupling thin film capacitor for mounting on an integrate circuit multi-layer ceramic. A bottom layer metallurgy (2) is evaporated or sputtered onto a carrier (1). A high dielectric layer (3) is deposited, followed by a top metallurgy (4) and an isolating layer (5). Via holes are etched to respective electrode layers, ball limiting metallurgy (6) deposited thereon followed by solder balls (7). The capacitor can be mounted onto a ceramic substrate face down in contact with a compatible footprint.

公开(公告)号：CA1126874A

公开(公告)日：1982-06-29

申请号：CA326900

申请日：1979-05-02

Applicant: IBM

Inventor： DOUGHERTY WILLIAM E

IPC: H01L23/498 ,  H01L23/538 ,  H05K1/00

Abstract: The coating of a conductor pattern on dielectric green sheets to a common edge thereof with stacking or superimpositioning together of a plurality of sheets to enclose the conductor pattern followed by sintering; with the eage side of the fired body having the exposed end terminations becoming the actual face of the body on which a semiconductor device is mounted in electrical circuit connection to respective ones of the common end terminations of the conductor runs. The opposite or distal ends of the conductor runs may be fanned out to the opposite edge of side of the fired body in increased spaced relationship to each other.

公开(公告)号：CA1182583A

公开(公告)日：1985-02-12

申请号：CA404031

申请日：1982-05-28

Applicant: IBM

Inventor： DOUGHERTY WILLIAM E ,  FEINBERG IRVING ,  HUMENIK JAMES N ,  PLATT ALAN

IPC: H01L27/04 ,  H01G2/06 ,  H01G4/06 ,  H01G4/10 ,  H01G4/12 ,  H01G4/228 ,  H01G4/30 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01G1/035 ,  H01G1/14

Abstract: THIN FILM DISCRETE DECOUPLING CAPACITOR A decoupling capacitor for mounting on an integrated circuit multi-layer ceramic. A bottom layer electrode, is evaporated or sputtered onto a carrier. A high dielectric layer is deposited followed by the upper metallurgy and a top isolating layer. Via holes are etched to respective electrode layers, ball limiting metalization deposited thereon followed by solder balls. The electrode is mounted onto the substrate, solder balls face down in contact with a compatible footprint.

公开(公告)号：CA1182582A

公开(公告)日：1985-02-12

申请号：CA404784

申请日：1982-06-09

Applicant: IBM

Inventor： DOUGHERTY WILLIAM E ,  GREER STUART E ,  NESTORK WILLIAM J ,  NORRIS WILLIAM T

IPC: H01L23/52 ,  H01L23/538

Abstract: AN IMPROVED SEMICONDUCTOR CHIP PACKAGE A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by personalized surface wiring and preset subsurface conductors.