公开(公告)号：AU552852B2

公开(公告)日：1986-06-26

申请号：AU1094083

申请日：1983-02-02

Applicant: IBM

Inventor： HEATH CHESTER A ,  DUREN RICHARD G VAN

IPC: G06F15/16 ,  G06F13/00 ,  G06F13/12 ,  G06F13/28 ,  G06F15/17 ,  G06F15/177 ,  G06F3/00

Abstract: A dual mode microprocessor acts either as a front-end IO controller processor relative to a primary host processor and device or as a secondary data processor having independent storage, processing and IO capabilities. Host software prepares a list of device control block (DCB) arrays, which contain primary commands interpretable by the microprocessor so as to evoke these modes. Each DCB contains a chaining bit permitting its interpretation sequence to be chained (or not chained) to another DCB sequence, and a mode bit defining either a high speed DI/DO (HS) mode of operation or a programmable offline (PO) mode. In HS mode the microprocessor conditions associated adapters to transfer a specified amount of data between the host memory and device, performing this transfer in an autonomous manner, i.e., without assistance from either processor. In PO mode the microprocessor directs associated elements to perform one or more programs of operations defined by secondary commands contained in a command list which is transferred to the microprocessor's memory by special PO mode "LOAD" type DCB's, and interpreted in response to special PO mode type "START" DCB's. A list transferred by one LOAD DCB may be repeatedly accessed at various positions by several START DCB's. The architecture of the command list includes commands which permit the microprocessor to exchange data with the host and/or a device, perform arithmetic operations on data, perform bit and byte manipulative operations on data, and directly control the device interface.

公开(公告)号：AU552910B2

公开(公告)日：1986-06-26

申请号：AU1078483

申请日：1983-01-26

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  HEATH CHESTER A ,  MEAD JUSTIN E ,  DUREN RICHARD G VAN ,  JANES GARY A

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00 ,  G06F13/00

Abstract: This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor. In another mode these lines permit a secondary system processor to exchange data with a series of multiplexed devices. Collectively, the interface lines have a symmetrical configuration which permits their use for direct interconnection of two data processing systems without the expense of additional "channel to channel" adaptation.

公开(公告)号：AU1078483A

公开(公告)日：1983-08-11

申请号：AU1078483

申请日：1983-01-26

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  HEATH CHESTER A ,  MEAD JUSTIN E ,  DUREN RICHARD G VAN ,  JANES GARY A

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00 ,  G06F13/00

Abstract: This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor. In another mode these lines permit a secondary system processor to exchange data with a series of multiplexed devices. Collectively, the interface lines have a symmetrical configuration which permits their use for direct interconnection of two data processing systems without the expense of additional "channel to channel" adaptation.