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公开(公告)号：JPH11175491A
公开(公告)日：1999-07-02
申请号：JP24160698
申请日：1998-08-27
Applicant: IBM
Inventor： ANDREWS LAWRENCE P , BECKMAN RICHARD CLYDE , ENG ROBERT CHIH-TSIN , LINGER JUDITH MARIE , PETTY JOSEPH C JR , SINIBALDI JOHN CLAUDE , TURBEVILLE GARY L , WILLIAMS KEVIN BRADLEY
IPC: G06F15/16 , G06F13/00 , G06F13/24 , G06F15/177 , H04L12/66 , G06F15/163
Abstract: PROBLEM TO BE SOLVED: To distribute the operation that processes transmission data of a primary speed by making a host processor read information from 2nd data memory when an interrupt is received. SOLUTION: Although 16-bits in a HBRIDGE interrupt register are usually used to represent different types of services up to sixteen, a digital signal processor(DSP) 12 sends a control block of data that represents an interrupt to be requested to a prescribed area in data memory of a controller card 4 by direct memory access process. Therefore, DSP subsystems 12 set a certain bit to send an interrupt through PCI buses 48 and 53. When the interrupt is received through an interrupt A line, a controller processor 53a decides that a DSP subsystem 12-0 requested the interrupt, and when the interrupt is received through an interrupt B line, it decides that one of DSPs 12-1 to 12-7 requested it.
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Patent Agency Ranking
公开(公告)号：AU552910B2
公开(公告)日：1986-06-26
申请号：AU1078483
申请日：1983-01-26
Applicant: IBM
Inventor： ANDREWS LAWRENCE P , HEATH CHESTER A , MEAD JUSTIN E , DUREN RICHARD G VAN , JANES GARY A
Abstract: This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor. In another mode these lines permit a secondary system processor to exchange data with a series of multiplexed devices. Collectively, the interface lines have a symmetrical configuration which permits their use for direct interconnection of two data processing systems without the expense of additional "channel to channel" adaptation.
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公开(公告)号：CA1184313A
公开(公告)日：1985-03-19
申请号：CA419287
申请日：1983-01-12
Applicant: IBM
Inventor： ANDREWS LAWRENCE P , HEATH CHESTER A , MEAD JUSTIN E , VAN DUREN RICHARD G , JANES GARY A
Abstract: PERIPHERAL ATTACHMENT INTERFACE FOR I/O CONTROLLER HAVING CYCLE STEAL AND OFF-LINE MODES This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor. In another mode these lines permit a secondary system processor to exchange data with a series of multiplexed devices. Collectively, the interface lines have a symmetrical configuration which permits their use for direct interconnection of two data processing systems without the expense of additional "channel to channel" adaptation.
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公开(公告)号：DE69836307T2
公开(公告)日：2007-04-26
申请号：DE69836307
申请日：1998-09-15
Applicant: IBM
Inventor： ANDREWS LAWRENCE P , BECKMAN RICHARD CLYDE , ENG ROBERT CHIH-TSIN , LINGER JUDITH MARIE , PETTY JOSEPH C , SINIBALDI JOHN CLAUDE , TURBEVILLE GARY L , WILLIAMS KEVIN BRADLEY
IPC: G06F13/24 , G06F15/16 , G06F13/00 , G06F15/177 , H04L12/66
Abstract: A pair of communications adapters each include a number of digital signal processors (12) and network interface circuits (24) for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor (2). Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.
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公开(公告)号：DE69836307D1
公开(公告)日：2006-12-14
申请号：DE69836307
申请日：1998-09-15
Applicant: IBM
Inventor： ANDREWS LAWRENCE P , BECKMAN RICHARD CLYDE , ENG ROBERT CHIH-TSIN , LINGER JUDITH MARIE , PETTY JOSEPH C , SINIBALDI JOHN CLAUDE , TURBEVILLE GARY L , WILLIAMS KEVIN BRADLEY
IPC: G06F13/24 , G06F15/16 , G06F13/00 , G06F15/177 , H04L12/66
Abstract: A pair of communications adapters each include a number of digital signal processors (12) and network interface circuits (24) for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor (2). Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.
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公开(公告)号：AU1078483A
公开(公告)日：1983-08-11
申请号：AU1078483
申请日：1983-01-26
Applicant: IBM
Inventor： ANDREWS LAWRENCE P , HEATH CHESTER A , MEAD JUSTIN E , DUREN RICHARD G VAN , JANES GARY A
Abstract: This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor. In another mode these lines permit a secondary system processor to exchange data with a series of multiplexed devices. Collectively, the interface lines have a symmetrical configuration which permits their use for direct interconnection of two data processing systems without the expense of additional "channel to channel" adaptation.
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