公开(公告)号：AU1078483A

公开(公告)日：1983-08-11

申请号：AU1078483

申请日：1983-01-26

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  HEATH CHESTER A ,  MEAD JUSTIN E ,  DUREN RICHARD G VAN ,  JANES GARY A

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00 ,  G06F13/00

Abstract: This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor. In another mode these lines permit a secondary system processor to exchange data with a series of multiplexed devices. Collectively, the interface lines have a symmetrical configuration which permits their use for direct interconnection of two data processing systems without the expense of additional "channel to channel" adaptation.

公开(公告)号：AU552910B2

公开(公告)日：1986-06-26

申请号：AU1078483

申请日：1983-01-26

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  HEATH CHESTER A ,  MEAD JUSTIN E ,  DUREN RICHARD G VAN ,  JANES GARY A

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00 ,  G06F13/00

Abstract: This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor. In another mode these lines permit a secondary system processor to exchange data with a series of multiplexed devices. Collectively, the interface lines have a symmetrical configuration which permits their use for direct interconnection of two data processing systems without the expense of additional "channel to channel" adaptation.

公开(公告)号：CA1184313A

公开(公告)日：1985-03-19

申请号：CA419287

申请日：1983-01-12

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  HEATH CHESTER A ,  MEAD JUSTIN E ,  VAN DUREN RICHARD G ,  JANES GARY A

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00

Abstract: PERIPHERAL ATTACHMENT INTERFACE FOR I/O CONTROLLER HAVING CYCLE STEAL AND OFF-LINE MODES This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor. In another mode these lines permit a secondary system processor to exchange data with a series of multiplexed devices. Collectively, the interface lines have a symmetrical configuration which permits their use for direct interconnection of two data processing systems without the expense of additional "channel to channel" adaptation.