公开(公告)号：JP2004318850A

公开(公告)日：2004-11-11

申请号：JP2004088448

申请日：2004-03-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ERIC E LETTER ,  SUTTON JOHN M

IPC: H04N5/44 ,  G06F1/12 ,  H04L7/02

CPC classification number: H04N21/426 ,  G06F1/12 ,  H04L7/0045 ,  H04L7/02

Abstract: PROBLEM TO BE SOLVED: To provide a method, system and synchronizing circuit for performing hardware component access to a set of data values without a limit. SOLUTION: Hardware-based synchronism is imparted within a device such as a set-top box so as to transmit the set of data values between a set of DCR registers each operating in a first frequency and a set of clock registers each operating in a second frequency. Concretely, in order to transmit a set of initial data values from the set of DCR registers to the set of clock registers, a control signal is expanded and then synchronized with a clock signal including the second frequency. In order to transmit a set of current data values from the set of clock registers to the set of DCR registers, the control signal is synchronized with a clock signal including the first frequency. The set of current data values is transmitted to a first register set, so that a hardware component (such as a CPU, for example, ) can perform access to the set of current data values without the limit. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2001290762A

公开(公告)日：2001-10-19

申请号：JP2001073048

申请日：2001-03-14

Applicant: IBM

Inventor： ERIC M FOSTER ,  STEVEN B HERNDON ,  ERIC E LETTER ,  RONALD S SVECK

IPC: G06F13/362 ,  G06F13/00 ,  G09G1/16 ,  G09G5/00

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for dynamically blocking access of a request signal to a shared bus. SOLUTION: The shared bus manages a request for access to an address space. A nonreal time master and a real time master compete about their requests for address space access by presenting the address access requests to the shared bus. An access dynamic block by R with respect to the shared bus is accomplished by using a request limiter. The request limiter is a device connected to a real time clock and uses algorithm for deciding a time when the access of R to the shared bus is made performable or nullified. The algorithm uses a window scheme that allows the access of R to the shared bus every N-th clock cycle. Here, the value of an integer N can be supplied to the request limiter by the real time master.