公开(公告)号：JPH10283797A

公开(公告)日：1998-10-23

申请号：JP8835198

申请日：1998-04-01

Applicant: IBM

Inventor： MARK W KELLOGG ,  TIMOTHY J DILL ,  ERIC L HEDBERG ,  BERTIN CLAUDE L

IPC: G06F12/16 ,  G06F11/10 ,  G11C7/10 ,  G11C11/401 ,  G11C29/42 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a high-band DRAM which can be used for an error detecting application. SOLUTION: A DRAM array 140 is divided into two or more subarrays 142, 144, 146, and 148. The subarrays are arranged in addressable lines and rows. When the DRAMs are programmed in a normal mode, the burst length becomes '8' and all address spaces of the DRAMs can be utilized for data storage. When the DRAMs are programmed for error detection (ECC mode), the burst length becomes '9' and the array is reconstituted at the part of the array which gives the ninth byte. The address spaces of the DRAMs are reduced by 1/8 in the ECC mode. It is preferable that all nine locations exist on the same page. Each page is divided into eight equal parts. In the normal mode, all of, the eight parts are assigned to the storage of data and, in the FCC mode, seven of the eights parts are assigned to the storage of data and the remaining one part is assigned to the storage of check bits.

公开(公告)号：JP2000030452A

公开(公告)日：2000-01-28

申请号：JP13222499

申请日：1999-05-13

Applicant: IBM

Inventor： DELL TIMOTHY J ,  ERIC L HEDBERG ,  MARK W KELLOGG

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To provide a memory device which stacks some commands, performs internally each command at an appropriate time, and thereby guarantees continuous input/output of data. SOLUTION: A clock counter controls the number of clock cycles to be generated before performing a command by this memory device. This memory device starts access to a memory directly or being delayed by the number of clocks controlled by the clock counter of a command while being controlled by a controller 22. As this memory device is operated as a slave of the controller 22, it cannot perform an instruction in a time other than the time controlled by the controller 22.

公开(公告)号：JPH10340224A

公开(公告)日：1998-12-22

申请号：JP13174498

申请日：1998-05-14

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  ERIC L HEDBERG

IPC: G11C11/407 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To provide a high performance/high band width RAM bus architecture that reduces the waiting time through the use of standard synchronous DRAM (SDRAM) chips. SOLUTION: The high performance/high band width memory bus architecture and module contain the standard synchronous DRAM(SDRAM) chips 12, and reduce the waiting time and the number of pins. Four bus pins detach an input command from data and establish a parallel system operation. An independent memory operation can be improved compared to a regular SDRAM operation by maintaining a 'packet'-type transaction. In the architecture, the bus is divided into command input and data input, which are detached from output data.