公开(公告)号：JPH11251538A

公开(公告)日：1999-09-17

申请号：JP539399

申请日：1999-01-12

Applicant: IBM

Inventor： TIMOTHY J DILL ,  KELLOGG MARK WILLIAM ,  BRUCE GERALD HAZELZETT

IPC: H01L27/10 ,  G11C5/00 ,  G11C5/06 ,  G11C8/12 ,  G11C11/401 ,  H05K1/11

Abstract: PROBLEM TO BE SOLVED: To obtain a module functioning as a DIMM or an SIMM when it is inserted into an old or new computer, respectively, by designing the module to emulate a DIMM or an SIMM, respectively, when it is inserted into a DIMM socket or an SIMM. SOLUTION: A DRAM array 27 and a path gate circuit 28 are mounted on a card 10 being interconnected electrically. When a specified edge on the card is inserted into a counterpart DIMM or SIMM socket mounted on a computer system board by selecting pads 22, 24, the path gate circuit is activated or inactivated selectively through selective bias thereof. Consequently, a module functions as an SIMM or a DIMM, respectively, when it is inserted into an SIMM socket or a DIMM socket.

公开(公告)号：JPH10283797A

公开(公告)日：1998-10-23

申请号：JP8835198

申请日：1998-04-01

Applicant: IBM

Inventor： MARK W KELLOGG ,  TIMOTHY J DILL ,  ERIC L HEDBERG ,  BERTIN CLAUDE L

IPC: G06F12/16 ,  G06F11/10 ,  G11C7/10 ,  G11C11/401 ,  G11C29/42 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a high-band DRAM which can be used for an error detecting application. SOLUTION: A DRAM array 140 is divided into two or more subarrays 142, 144, 146, and 148. The subarrays are arranged in addressable lines and rows. When the DRAMs are programmed in a normal mode, the burst length becomes '8' and all address spaces of the DRAMs can be utilized for data storage. When the DRAMs are programmed for error detection (ECC mode), the burst length becomes '9' and the array is reconstituted at the part of the array which gives the ninth byte. The address spaces of the DRAMs are reduced by 1/8 in the ECC mode. It is preferable that all nine locations exist on the same page. Each page is divided into eight equal parts. In the normal mode, all of, the eight parts are assigned to the storage of data and, in the FCC mode, seven of the eights parts are assigned to the storage of data and the remaining one part is assigned to the storage of check bits.