公开(公告)号：JP2008165772A

公开(公告)日：2008-07-17

申请号：JP2007322378

申请日：2007-12-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LASTRAS-MONTANO LUIS A ,  DELL TIMOTHY J

IPC: G06F12/16 ,  G06F11/08

CPC classification number: G11C29/56008 ,  G06F11/1012 ,  G11C5/04 ,  G11C2029/0409

Abstract: PROBLEM TO BE SOLVED: To provide a method and system for improving maintenability of a memory system. SOLUTION: The method for identifying a faulty memory element in the memory system wherein two or more modules operate in unison in response to a read request, includes a step (S810) of receiving syndrome bits and an address associated with an uncorrectable error (UE). And, the method further includes a step of, in response to a previous correctable error (CE) having occurred, retrieving the location of the CE specifying a memory device position, a step of determining a location of the UE specifying a memory device position by using the location of the CE and the syndrome bits of the UE as input, and a step (S816) of identifying the faulty memory element associated with the location of the UE. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于改善存储系统的可维护性的方法和系统。 解决方案：用于识别存储器系统中的错误存储元件的方法，其中两个或更多个模块响应于读取请求而一致地操作，包括接收校正子位和与不可校正错误相关联的地址的步骤（S810） （UE）。 并且，该方法还包括响应于发生的先前可校正错误（CE）的响应，检索指定存储器设备位置的CE的位置的步骤，确定UE指定存储器设备位置的位置的步骤 使用CE的位置和UE的校正子位作为输入，以及识别与UE的位置相关联的故障存储器元件的步骤（S816）。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2000339216A

公开(公告)日：2000-12-08

申请号：JP2000124596

申请日：2000-04-25

Applicant: IBM

Inventor： DELL TIMOTHY J ,  HAZELZET BRUCE G ,  KELLOGG MARK W ,  MILLER CHRISTOPHER P

IPC: G06F1/32 ,  G06F12/02 ,  G06F12/06 ,  G11C11/403

Abstract: PROBLEM TO BE SOLVED: To provide an improved memory module with a signal processing element, preferably a DSP, at least one bank of a memory chip, preferably first and second banks to be individually addressed and its use in a computer system. SOLUTION: The memory module 8 is provided with first and second banks 12, 13 to be respectively addressed of the DSP of the memory chip. The first bank is constituted so as to basically function under control of the signal processing element 36, the second bank is constituted so as to basically function under control of a system memory controller 28, however, all parts of respective memory banks are addressed by both of the signal processing element and the system memory controller. Both banks of the memory chip is placed on at least one high power state and at least one low power state by either of the system memory controller or the DSP.

公开(公告)号：JP2000030452A

公开(公告)日：2000-01-28

申请号：JP13222499

申请日：1999-05-13

Applicant: IBM

Inventor： DELL TIMOTHY J ,  ERIC L HEDBERG ,  MARK W KELLOGG

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To provide a memory device which stacks some commands, performs internally each command at an appropriate time, and thereby guarantees continuous input/output of data. SOLUTION: A clock counter controls the number of clock cycles to be generated before performing a command by this memory device. This memory device starts access to a memory directly or being delayed by the number of clocks controlled by the clock counter of a command while being controlled by a controller 22. As this memory device is operated as a slave of the controller 22, it cannot perform an instruction in a time other than the time controlled by the controller 22.

公开(公告)号：JP2006048690A

公开(公告)日：2006-02-16

申请号：JP2005220597

申请日：2005-07-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DELL TIMOTHY J ,  GOWER KEVIN C ,  KARK KEVIN W ,  MARK W KELLOGG ,  MAULE WARREN E

IPC: G06F13/16 ,  G06F12/00

CPC classification number: G06F13/4243 ,  G06F13/1684

Abstract: PROBLEM TO BE SOLVED: To provide a memory system realizing a bus speed multiplier. SOLUTION: This memory system has at least one memory module operating at a data transfer speed of the memory module. The memory system also has a memory controller and at least one memory bus. The memory bus operates at a data transfer speed four times the data transfer speed of the memory module. The memory controller and the memory module are connected to each other by a packet type multitransfer interface via the memory bus. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供实现总线速度倍增器的存储器系统。 解决方案：该存储器系统具有以存储器模块的数据传输速度操作的至少一个存储器模块。 存储器系统还具有存储器控制器和至少一个存储器总线。 存储器总线的数据传输速度是存储器模块的数据传输速度的四倍。 存储器控制器和存储器模块通过存储器总线通过分组类型的多传输接口相互连接。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006048688A

公开(公告)日：2006-02-16

申请号：JP2005220421

申请日：2005-07-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DELL TIMOTHY J ,  FERRAIOLO FRANK D ,  GOWER KEVIN C ,  KARK KEVIN W ,  MARK W KELLOGG ,  MAULE WARREN E

IPC: G06F12/16

CPC classification number: G06F11/201 ,  G06F11/104

Abstract: PROBLEM TO BE SOLVED: To provide a memory system spared in a segment level. SOLUTION: This memory system includes a cascade type interconnection system spared in the segment level. The cascade type interconnection system has at least two memory assemblies and a memory bus. The memory bus has a plurality of segments, and the memory assemblies are connected to each other via the memory bus. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供在段级别中节省的存储器系统。

解决方案：该存储器系统包括在段级别中节省的级联型互连系统。 级联型互连系统具有至少两个存储器组件和存储器总线。 存储器总线具有多个段，并且存储器组件经由存储器总线相互连接。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2000231534A

公开(公告)日：2000-08-22

申请号：JP2000012794

申请日：2000-01-21

Applicant: IBM

Inventor： DELL TIMOTHY J ,  STEVEN A GRANDON ,  MARK W KELLOGG

IPC: G06F3/00 ,  G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C5/00 ,  G11C7/00 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To obtain a single memory system which can be applied to either a 3.3V DIM or a DDR DIMM by allowing a data storage device to selectively apply each termination to each data inquiry line as necessary. SOLUTION: A DIM identifying circuit means 77 is provided in a memory controller 16b for identifying the kind of a DIMM inserted into a memory 10, and for transmitting a switch activation pulse through a strobe line 78 to termination boards 67 and 68 when it is judged that a DDR DIMM is inserted into the memory 10. The DIMM is provided with an identifying means such as a PROM circuit to be integrated into each DIMM at the time of manufacturing regardless of the kind of the DIMM, that is, 3.3V DIMM or DDR DIMM. Therefore, the kind of the DIMM inserted into the memory 10, that is, 3.3V DIMM or DDR DIMM can be identified by the DIMM identifying circuit means 77.

公开(公告)号：DE69924179T2

公开(公告)日：2006-03-23

申请号：DE69924179

申请日：1999-04-29

Applicant: IBM

Inventor： DELL TIMOTHY J ,  HEDBERG ERIK L ,  KELLOGG MARK W

IPC: G11C7/00 ,  G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401

Abstract: A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.

公开(公告)号：DE69924179D1

公开(公告)日：2005-04-21

申请号：DE69924179

申请日：1999-04-29

Applicant: IBM

Inventor： DELL TIMOTHY J ,  HEDBERG ERIK L ,  KELLOGG MARK W

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C7/00

Abstract: A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.