公开(公告)号：CA1023876A

公开(公告)日：1978-01-03

申请号：CA210639

申请日：1974-10-03

Applicant: IBM

Inventor： COOK HERBERT C ,  FARRAR PAUL A ,  HALLEN ROBERT L

IPC: H05K3/24 ,  H01B1/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/52 ,  H01L23/532 ,  H05K3/38 ,  H05K3/46

Abstract: Disclosed is a method for the manufacture of composite thin films useful among other applications as electronic microcircuit interconnections, fuses, and contacts, terminal pads and voltage distribution ring metallurgy comprising in carrying out an integral circuit fabrication process the steps of first depositing a barrier layer of antidiffusion material, such as chromium, followed by superimposing thereon a film of highly conductive metals susceptible to corrosion and followed by the deposition of a highly corrosive resistant metal film. A subtractive etch pattern is formed in the composite metal film followed by heating the structure to an elevated temperature for a predetermined period of time so that the uppermost layer of the composite flows by diffusion over the edge section to protect the conductive metal film from corrosive effects.

公开(公告)号：FR2286505A1

公开(公告)日：1976-04-23

申请号：FR7525150

申请日：1975-08-07

Applicant: IBM

Inventor： ALBERTS GENE S ,  FARRAR PAUL A ,  HALLEN ROBERT L

IPC: G11C17/00 ,  G11C11/24 ,  G11C11/404 ,  H01L21/00 ,  H01L23/29 ,  H01L23/525 ,  H01L27/10 ,  H01L21/88 ,  H01L21/72

Abstract: Disclosed is an improved method for manufacturing semiconductor integrated circuitry whereby interconnection pad limiting metallurgy and read only fusible link memory structure is simultaneously formed by first blank depositing a composite metal film followed by in situ forming pad metallurgy and said read only link structure utilizing photoresist and etch techniques. Said read only memory link structure is utilized for directing the use of redundant lines in place of defective array bits.

公开(公告)号：CA1168916A

公开(公告)日：1984-06-12

申请号：CA400827

申请日：1982-04-13

Applicant: IBM

Inventor： FARRAR PAUL A ,  GEFFKEN ROBERT M ,  KROLL CHARLES T

IPC: H01L23/522 ,  H01L21/027 ,  H01L21/28 ,  H01L21/768 ,  H05K3/07

Abstract: A method for providing high density multiple level metallurgy for integrated circuit devices in which a relatively thin layer of plasma produced silicon nitride is deposited over a first level of interconnection metallurgy formed on a layer of silicon oxide. Overlap via holes are etched in the nitride layer followed by deposition of a thicker layer of polyimide forming polymer. A second set of via holes larger than the first are provided in the polymer layer and a second layer of interconnection metallurgy is then deposited by a lift-off deposition technique. BU9-79-015

公开(公告)号：CA974660A

公开(公告)日：1975-09-16

申请号：CA145359

申请日：1972-06-22

Applicant: IBM

Inventor： FARRAR PAUL A

IPC: H01L21/00 ,  H01L23/532

Abstract: An electrical interconnection contact structure including a layer containing a major proportion of an intermetallic compound contacting the surface of an integrated circuit device. The intermetallic layer is covered by a layer of conductive alloy which includes a major proportion of a solid solution of the same chemical elements as the intermetallic compound. One of the chemical elements is preferred to be an electromigration preventing dopant. Two methods of creating such a contact structure are disclosed including a sandwich technique where a layer of a first element and a layer of a second element form the intermetallic compound and a co-deposition technique where the first and second elements are co-deposited as the intermetallic compound. An alternative embodiment includes causing the intermetallic layer to spheroidize after exposure to high temperature stress allowing the major ingredient of the overlying layer to contact the semiconductor surface between spheroids. The invention provides an effective method of controlling spiking of shallow semiconductor junctions while improving the electromigration characteristics of the conductive member.