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    METHOD FOR FORMING SELF-ALIGNED COPPER DIFFUSION BARRIER IN VIA
    2.
    发明专利
    METHOD FOR FORMING SELF-ALIGNED COPPER DIFFUSION BARRIER IN VIA 失效

    公开(公告)号：JPH10340865A

    公开(公告)日：1998-12-22

    申请号：JP11653798

    申请日：1998-04-27

    Applicant: IBM

    Inventor： GEFFKEN ROBERT M ,  STEPHEN E LUCE

    IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

    Abstract: PROBLEM TO BE SOLVED: To prevent copper from cansing corrosion on an interlevel dielectric oxide or other insulators, by etching a copper conductor wherein a via is formed in a dielectric layer in a substrate, in a directional etching step, and filling the via on the dielectric layer and the copper conductor with a conductor. SOLUTION: Oxide copper 4 is formed on the exposed surface of a copper wire 3 as a substrate, and an interlevel dielectric 2 wherein a via 1 is formed on the copper wire 3 is so laminated that the oxide copper 4 is exposed. After barrier material 5 is stuck on the surfaces of the interlevel dielectric 2, a side wall 6 and the oxide copper 4, the barrier material 5 is eliminated from the upper surface of the interlevel dielectric 2 by directional etching, and the barrier material 5 and the oxide copper 4 are eliminated from the bottom part of the via 1. After that, the via 1 in the interlevel dielectric 2 is filled with copper. Thereby oxide of the interlevel dielectric 2 or other insulators can be prevented from corrosion caused by the copper conductor.

    ADJUSTABLE SELF-ALIGNED AIR GAP DIELECTRIC FOR LOW CAPACITANCE WIRING
    3.
    发明申请
    ADJUSTABLE SELF-ALIGNED AIR GAP DIELECTRIC FOR LOW CAPACITANCE WIRING 审中-公开
    可调自适应空气隙电介质用于低电容接线

    公开(公告)号：WO2005034200A2

    公开(公告)日：2005-04-14

    申请号：PCT/US2004032404

    申请日：2004-09-30

    Applicant: IBM ,  GEFFKEN ROBERT M ,  MOTSIFF WILLIAM T

    Inventor： GEFFKEN ROBERT M ,  MOTSIFF WILLIAM T

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L

    CPC classification number: H01L21/76831 ,  H01L21/76811 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An adjustable self aligned low capacitance integrated circuit air gap structure comprises a first interconnect (64a) adjacent a second interconnect (64b) on an interconnect level, spacers (60b, 60c) formed along adjacent sides of the first and second interconnects, and an air gap (68) formed between the first and second interconnects. The air gap extends above an upper surface (74a, 74b) of at least one of the first and second interconnects and below a lower surface (76a, 76b) of at least one of the first and second interconnects, and the distance between the spacers defines the width of the air gap. The air gap is self-aligned to the adjacent sides of the first and second interconnects.

    Abstract translation: 可调整的自对准低电容集成电路气隙结构包括邻近互连层上的第二互连（64b）的第一互连（64a），沿第一和第二互连的相邻侧形成的间隔物（60b，60c） 间隙（68）形成在第一和第二互连之间。 空气间隙延伸到第一和第二互连中的至少一个的上表面（74a，74b）上方，并且位于第一和第二互连中的至少一个互连的下表面（76a，76b）的下方以及间隔件之间的距离 定义气隙的宽度。 气隙与第一和第二互连的相邻侧自对准。

    CAPACITOR STRUCTURE AND ITS MANUFACTURING METHOD
    4.
    发明专利
    CAPACITOR STRUCTURE AND ITS MANUFACTURING METHOD 失效

    公开(公告)号：JP2001313373A

    公开(公告)日：2001-11-09

    申请号：JP2001098235

    申请日：2001-03-30

    Applicant: IBM

    Inventor： KERRY BERNSTEIN ,  GEFFKEN ROBERT M ,  STAMPER ANTHONY K ,  STEVEN A SAINT ONGE

    IPC: H01L23/52 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To provide a metal capacitor installed on a chip. SOLUTION: Capacitors (60, 126) manufactured on a semiconductor chip have strap/contacts (41A, 119A), which mutually connect bottom plates (41B, 111A) of a capacitor to a chip circuit. In one version, an extension part of a material, constituting a bottom plate of a capacitor forms a strap contact. In the other version, a capacitor (185) comprises a folded bottom plate, which uses an available space and therefore increases its capacitance, a dielectric layer and a top plate. By means of a plurality of manufacturing methods, manufacturing of these capacitors of various versions can be incorporated in a standard dual or single-damascene manufacturing process, including a copper damascene process.

    ANTIFUSE STRUCTURE AND ITS FABRICATION PROCESS
    5.
    发明专利
    ANTIFUSE STRUCTURE AND ITS FABRICATION PROCESS 失效

    公开(公告)号：JPH10335465A

    公开(公告)日：1998-12-18

    申请号：JP11651698

    申请日：1998-04-27

    Applicant: IBM

    Inventor： BHATTACHARYYA ARUP ,  GEFFKEN ROBERT M ,  LAM CHUNG H ,  LEIDY ROBERT K

    IPC: H01L21/82 ,  H01L23/525

    Abstract: PROBLEM TO BE SOLVED: To provide an antifuse structure and method for personalizing a semiconductor device which can overcome the limitations of the prior art. SOLUTION: An antifuse 100 of the preferred embodiment comprises a two layer transformble insulator core between two electrodes 102, 104. The transformable insulator core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes 102, 104. The two layer core preferably comprises an injector layer 106 and a dielectric layer 108. The injector layer 106 preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer 106 and the dielectric layer 108 are non-conductive. When a sufficient voltage is applied, the core fuses together and becomes conductive.

    Buried metal dual damascene plate capacitor
    6.
    发明专利
    Buried metal dual damascene plate capacitor 未知

    公开(公告)号：GB2366077A

    公开(公告)日：2002-02-27

    申请号：GB0105197

    申请日：2001-03-02

    Applicant: IBM

    Inventor： GEFFKEN ROBERT M ,  STAMPER ANTHONY K

    IPC: H01L21/02 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L29/92

    Abstract: A metal capacitor is formed as part of metal dual damascene process in the making of a wafer. A lower plate (27) of the capacitor is sandwiched between an insulating layer (25) and a dielectric layer (29). The insulating layer on an opposite side abuts a layer of metallization (23, 24) and the dielectric layer separates the lower plate of the capacitor from an upper plate (59) of the capacitor. A portion (27A) of the lower plate projects into a via (37) adjacent to it that is filled with copper (63) and possibly a barrier layer (51A). The via projects up to a common surface with the upper plate but is electrically isolated from the upper plate. The via also extends down to the layer of metallization. The capacitor may include a high-k dielectric. Methods of making the capacitor are described.

    Buried metal dual damascene plate capacitor
    7.
    发明专利
    Buried metal dual damascene plate capacitor 未知

    公开(公告)号：GB2366077B

    公开(公告)日：2005-01-19

    申请号：GB0105197

    申请日：2001-03-02

    Applicant: IBM

    Inventor： GEFFKEN ROBERT M ,  STAMPER ANTHONY K

    IPC: H01L21/02 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L29/92

    Abstract: A metal capacitor formed as part of metal dual damascene process in the BEOL, of a wafer. A lower plate (27) of the capacitor is sandwiched between an insulating layer (25) and a dielectric layer (29). The insulating layer on an opposite side abuts a layer of metalization (23, 24) and the dielectric layer separates the lower plate of the capacitor from an upper plate (59) of the capacitor. A portion (27A) of the lower plate projects into a via (37) adjacent to it that is filled with copper (63). The via projects up to a common surface with the upper plate but is electrically isolated form the upper plate. The via also extends down to the layer of metalization.

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