公开(公告)号：JP2004080036A

公开(公告)日：2004-03-11

申请号：JP2003292574

申请日：2003-08-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  FENG GEORGE C ,  HARPER JAMES M E ,  LEWIS L SUU

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/4991 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/6659

Abstract: PROBLEM TO BE SOLVED: To provide a method for improving performance in a microelectronic circuit. SOLUTION: A method and a structure for an integrated circuit transistor include a gate conductor having a first conductive material and a second material. The structure has a spacer that is adjacent to the gate conductor and cannot be deformed, and the gap between the gate conductor and the spacer. The first conductive material can be polysilicon, and the second material can be either metal or a polymer. The second material operates as a place holder for the gap. An environmental gas is contained by the gap, and resistance in the gate conductor is reduced. COPYRIGHT: (C)2004,JPO

公开(公告)号：JPH11149772A

公开(公告)日：1999-06-02

申请号：JP23402398

申请日：1998-08-20

Applicant: IBM

Inventor： DELL TIMOTHY JAY ,  FENG GEORGE C ,  KELLOGG MARK W

IPC: G11C11/407 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H05K1/02 ,  H05K1/14

Abstract: PROBLEM TO BE SOLVED: To provide a synchronous dynamic random access memory which has two banks of connectors which accommodate single or dual in-line memory modules. SOLUTION: A clock 28 is provided near connectors 12-26 and generates a clock signal with a known rising time. Clock wirings 30 are provided between the clock and the connectors and module wirings transmit clock pulses from the connectors to a memory. The lengths and impedances of the wirings are so selected as to have the round-trip delay time of the clock pulse between the clock and the memory smaller than the known rise time of the clock pulse. It is recommended that the clock is provided between two banks of connectors to minimize the wiring lengths and reduce coupling noises.

公开(公告)号：CA1041227A

公开(公告)日：1978-10-24

申请号：CA254707

申请日：1976-06-11

Applicant: IBM

Inventor： FENG BAI-CWO ,  FENG GEORGE C

IPC: H01L21/76 ,  H01L21/32 ,  H01L21/762 ,  H01L21/94

Abstract: A METHOD FOR FORMING DIELECTRIC ISOLATION COMBINING DIELECTRIC DEPOSITION AND THERMAL OXIDATION of Invention In the fabrication of integrated circuits, a method is provided for forming recessed silicon dioxide isolation in which the "bird's beak" problem associated with conventional silicon dioxide-silicon nitride composite masking structures is minimized. A conventional composite mask comprising a bottom layer of silicon dioxide and an upper layer of silicon nitride having a plurality of openings defining the regions in the silicon substrate which are to be thermally oxidized is formed on the substrate. Recesses are then etched in the silicon substrate in registration with the openings in the composite mask. The silicon dioxide layer should be, in effect, over-etched to extend the openings in the silicon dioxide to greater lateral dimensions than the openings in the silicon nitride layer whereby the silicon nitride layer at the periphery of the openings is undercut. A layer of a material capable of blocking the oxidation of silicon and having a greater etchability than silicon nitride is then deposited in said recesses and covering said undercut portions of said silicon nitride masks. At this point the structure is blanket etched to remove said blocking material from the portions of the recesses not under said silicon nitride and to, thereby, expose the silicon in these portions. Finally, the structure is thermally oxidized so that the exposed silicon in the recesses oxidizes to form recessed regions of silicon dioxide substantially coplanar with the unrecessed regions of the silicon substrate. Because of the undercutting and the deposition in the undercut portions of the recesses of the blocking material, the "bird's beak" effect is minimized.

公开(公告)号：FR2316733A1

公开(公告)日：1977-01-28

申请号：FR7616134

申请日：1976-05-21

Applicant: IBM

Inventor： FENG BAI-CWO ,  FENG GEORGE C

IPC: H01L21/76 ,  H01L21/32 ,  H01L21/762

Abstract: In the fabrication of integrated circuits, a method is provided for forming recessed silicon dioxide isolation in which the "bird's beak" problem associated with conventional silicon dioxide-silicon nitride composite masking structures is minimized. A conventional composite mask comprising a bottom layer of silicon dioxide and an upper layer of silicon nitride having a plurality of openings defining the regions in the silicon substrate which are to be thermally oxidized is formed on the substrate. Recesses are then etched in the silicon substrate in registration with the openings in the composite mask. The silicon dioxide layer should be, in effect, over-etched to extend the openings in the silicon dioxide to greater lateral dimensions than the openings in the silicon nitride layer whereby the silicon nitride layer at the periphery of the openings is undercut.