中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.017 seconds)

    METHOD OF FORMING VERY SMALL IMPURITY REGIONS IN A SEMICONDUCTOR SUBSTRATE
    6.
    发明专利
    METHOD OF FORMING VERY SMALL IMPURITY REGIONS IN A SEMICONDUCTOR SUBSTRATE 未知

    公开(公告)号：DE2860161D1

    公开(公告)日：1980-12-18

    申请号：DE2860161

    申请日：1978-06-02

    Applicant: IBM

    Inventor： FENG BAI-CWO ,  FENG GEORGE CHENG-CWO

    IPC: H01L29/73 ,  H01L21/033 ,  H01L21/31 ,  H01L21/314 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/00 ,  H01L21/82

    Abstract: A method of forming extremely small impurity regions within other impurity regions without the need for providing critical masks. In the preferred embodiment this is achieved by forming an undercut band within masking layers atop a substrate to define a first impurity region, such as the base region of a bipolar transistor. After this region is formed by the introduction of impurities, the undercut is filled-in by a chemical vapor deposition process. A blocking mask may then be used for the formation of the second impurity region, in this case the emitter, within the first region. The window of the second region is defined by the filled-in band, thereby insuring a selected distance between the peripheries of said first and second impurity regions. The same mask may also be used to form other self-aligned regions with the first region.

    FORMING FEEDTHROUGH CONNECTIONS FOR MULTILEVEL INTERCONNECTION METALLURGY EMS
    7.
    发明专利
    FORMING FEEDTHROUGH CONNECTIONS FOR MULTILEVEL INTERCONNECTION METALLURGY EMS 未知

    公开(公告)号：CA1079683A

    公开(公告)日：1980-06-17

    申请号：CA275384

    申请日：1977-03-30

    Applicant: IBM

    Inventor： FENG BAI-CWO ,  LECHATON JOHN S

    IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  C23C15/00

    Abstract: FORMING FEEDTHROUGH CONNECTIONS FOR MULTI-LEVEL INTERCONNECTION METALLURGY SYSTEMS A method for forming feedthrough connections, or via studs, between levels of metallization atop semiconductor substrates. A first level conductive pattern is formed atop the substrate. A feedthrough pattern is then formed atop the first conductive pattern, the feedthrough pattern including one or more metal studs and a second, expendable material disposed on the studs. The formation of the feedthrough pattern is preferably accomplished by a lift-off process. The expendable material is removable by an etchant which does not substantially attack either the metal or the substrate. An insulator is deposited atop the substrate and the pattern by RF sputtering at a bias which is sufficiently high to cause substantial reemission of the insulator, thereby covering the exposed substrate surfaces and the expendable material but leaving the side surfaces of the material exposed. The expendable material is then etched with said etchant, thereby removing the second material and the portion of the insulator disposed thereon. A second conductive pattern may then be formed atop the insulator and selectively connected to the feedthroughs which thereby provide the interconnection between the first and second levels.

    8.
    发明专利
    未知

    公开(公告)号：FR2316733A1

    公开(公告)日：1977-01-28

    申请号：FR7616134

    申请日：1976-05-21

    Applicant: IBM

    Inventor： FENG BAI-CWO ,  FENG GEORGE C

    IPC: H01L21/76 ,  H01L21/32 ,  H01L21/762

    Abstract: In the fabrication of integrated circuits, a method is provided for forming recessed silicon dioxide isolation in which the "bird's beak" problem associated with conventional silicon dioxide-silicon nitride composite masking structures is minimized. A conventional composite mask comprising a bottom layer of silicon dioxide and an upper layer of silicon nitride having a plurality of openings defining the regions in the silicon substrate which are to be thermally oxidized is formed on the substrate. Recesses are then etched in the silicon substrate in registration with the openings in the composite mask. The silicon dioxide layer should be, in effect, over-etched to extend the openings in the silicon dioxide to greater lateral dimensions than the openings in the silicon nitride layer whereby the silicon nitride layer at the periphery of the openings is undercut.

    9.
    发明专利
    未知

    公开(公告)号：DE2626738A1

    公开(公告)日：1977-01-20

    申请号：DE2626738

    申请日：1976-06-15

    Applicant: IBM

    Inventor： FENG BAI-CWO ,  FENG GEORGE CHENG-CWO

    IPC: H01L21/76 ,  H01L21/32 ,  H01L21/762

    Abstract: In the fabrication of integrated circuits, a method is provided for forming recessed silicon dioxide isolation in which the "bird's beak" problem associated with conventional silicon dioxide-silicon nitride composite masking structures is minimized. A conventional composite mask comprising a bottom layer of silicon dioxide and an upper layer of silicon nitride having a plurality of openings defining the regions in the silicon substrate which are to be thermally oxidized is formed on the substrate. Recesses are then etched in the silicon substrate in registration with the openings in the composite mask. The silicon dioxide layer should be, in effect, over-etched to extend the openings in the silicon dioxide to greater lateral dimensions than the openings in the silicon nitride layer whereby the silicon nitride layer at the periphery of the openings is undercut.

Patent Agency Ranking