公开(公告)号：WO2008052858B1

公开(公告)日：2008-07-31

申请号：PCT/EP2007060639

申请日：2007-10-08

Applicant: IBM ,  IBM UK ,  DELL TIMOTHY JAY ,  GLAISE RENE

Inventor： DELL TIMOTHY JAY ,  GLAISE RENE

IPC: H04L1/00 ,  H04L25/03

CPC classification number: H04L25/03866 ,  H03M13/03 ,  H03M13/27 ,  H04L1/0042 ,  H04L1/0057 ,  H04L1/0071

Abstract: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x) = x 10 + x 3 + 1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x) = x 6 + 1.

Abstract translation: 前向纠错（FEC）码与64B / 66B编码标准在串行器/解串器（SerDes）通信链路上传输时使用的自同步扰码器兼容。 FEC码允许编码和解码分别在加扰之前和之后发生，以便保持对发送信号的加扰操作的属性。 尽管由于64B / 66B加扰过程导致的所有传输错误的三倍，该代码仍允许纠正任何单个传输错误。 汉明码与度为n的比特交织奇偶校验码（BIP-n）组合。 这两个代码既提供了对数据包最大长度的任何错误的保护，也提供了通过解扰过程复制两次或三次的错误的保护。 所有单比特错误，无论是否倍增，都具有独特的综合征，因此易于纠正。 另外，数据包可以通过多个串行链路传输，以实现更高带宽应用，而不会降低代码效率。 汉明码可以由任何不可约多项式产生，例如H（x）= x 10 + x 3 + 1 + BIP码被选择为6度 以适合64B / 66B加扰多项式并由B（x）= x + 6 + 1表示。

公开(公告)号：WO2008052858A2

公开(公告)日：2008-05-08

申请号：PCT/EP2007060639

申请日：2007-10-08

Applicant: IBM ,  IBM UK ,  DELL TIMOTHY JAY ,  GLAISE RENE

Inventor： DELL TIMOTHY JAY ,  GLAISE RENE

IPC: H04L1/00 ,  H04L25/03

CPC classification number: H04L25/03866 ,  H03M13/03 ,  H03M13/27 ,  H04L1/0042 ,  H04L1/0057 ,  H04L1/0071

Abstract: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x) = x 10 + x 3 + 1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x) = x 6 + 1.

公开(公告)号：JPH10188554A

公开(公告)日：1998-07-21

申请号：JP30702997

申请日：1997-11-10

Applicant: IBM

Inventor： CONNOLLY BRIAN J ,  DELL TIMOTHY JAY ,  HAZELZET BRUCE GERARD ,  KELLOGG MARK WILLIAM

IPC: G11C11/406 ,  G11C11/401 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To make both CBR and hidden refreshing executable on a DRAM forming a SIMM or a DIMM, by converting each one system RAS and CAS signal into a plurality of RAS and CAS signals for normal read/write operation on the DRAM. SOLUTION: An ASIC chip 78 converts a SYS-RAS signal into RAS-T or RAS-B signals by a signal of a pin A12 or an SYS-CAS signal to CAS-L or CAS-R signals using an address on a pin A10 separately. A RAS sample latch 90 determines whether the cycle corresponds to CBR or not by a signal from a receiver 80 to perform a CBR refreshing or a normal reading/writing. An RAS address latch 92 and a CAS sample latch 96 determine a hidden refreshing by signals from receivers 82 and 84 and an inverter 94 to execute. This accomplishes both of the CBR and the hidden refreshing on a DRAM.

公开(公告)号：JP2000207073A

公开(公告)日：2000-07-28

申请号：JP34063799

申请日：1999-11-30

Applicant: IBM

Inventor： DELL TIMOTHY JAY ,  PRICER WILBUR DAVID

IPC: G06F3/00 ,  H04L25/02 ,  H04L25/14

Abstract: PROBLEM TO BE SOLVED: To provide a bus system capable of transmitting n-bit data. SOLUTION: A fast bus architecture is characterized in a low signal level, differential detection and the net current sum of zeros on a group of four wire transmission lines. This bus system is provided with a system for transmitting n-bit data, has an encoding system 12 which receives the n-bit data and outputs (m) pieces of signals (net current sum is zero), has (m) pieces of transmission lines 16 on which (m) pieces of signals are transferred and has a decoding system 18 which receives the (m) pieces of signals and converts them into n-bit data by using a differential amplifier.

公开(公告)号：JPH11149772A

公开(公告)日：1999-06-02

申请号：JP23402398

申请日：1998-08-20

Applicant: IBM

Inventor： DELL TIMOTHY JAY ,  FENG GEORGE C ,  KELLOGG MARK W

IPC: G11C11/407 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H05K1/02 ,  H05K1/14

Abstract: PROBLEM TO BE SOLVED: To provide a synchronous dynamic random access memory which has two banks of connectors which accommodate single or dual in-line memory modules. SOLUTION: A clock 28 is provided near connectors 12-26 and generates a clock signal with a known rising time. Clock wirings 30 are provided between the clock and the connectors and module wirings transmit clock pulses from the connectors to a memory. The lengths and impedances of the wirings are so selected as to have the round-trip delay time of the clock pulse between the clock and the memory smaller than the known rise time of the clock pulse. It is recommended that the clock is provided between two banks of connectors to minimize the wiring lengths and reduce coupling noises.

公开(公告)号：DE69432890T2

公开(公告)日：2004-05-27

申请号：DE69432890

申请日：1994-11-09

Applicant: IBM

Inventor： DELL TIMOTHY JAY ,  FENG GEORGE CHENG-CWO ,  KELLOGG MARK WILLIAM

IPC: G11C11/401 ,  G06F1/10 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G11C5/00 ,  G11C7/22 ,  G11C11/407 ,  H01L25/10 ,  H01L25/18 ,  H05K1/02 ,  H05K1/11

Abstract: A packaging assembly for semiconductor memory modules using synchronous clocking signals distributed to each module within a package. The clock distribution network on the assembly is characterized by including a transmission line termination means, preferably a resistor, coupled immediately adjacent to one of the assembly input pins.

公开(公告)号：SG77255A1

公开(公告)日：2000-12-19

申请号：SG1999003392

申请日：1999-07-15

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  KELLOGG MARK WILLIAM ,  HEDBERG ERIK L ,  DELL TIMOTHY JAY

IPC: G06F13/16 ,  G06F13/38 ,  H01L21/8242

Abstract: A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.

公开(公告)号：SG64449A1

公开(公告)日：1999-04-27

申请号：SG1997003733

申请日：1997-10-14

Applicant: IBM

Inventor： DELL TIMOTHY JAY ,  KELLOGG MARK WILLIAM

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F12/16

Abstract: Reduced specification DRAMs are used in memory assemblies in such a way as to maximize the use of the good cells in the reduced specification DRAM chips. An external memory array is mapped to replace defective memory locations on a real time basis. The major components are (1) a non-volatile storage device, (2) a logic device, and (3) a volatile storage device. The non-volatile storage device, such as an EPROM, EEPROM, or a flash memory chip, is used to retain address information for all memory fails on a given assembly. In simpler implementations, the use of specific combinations of RAM failure types can be used in addition to a logic decode chip, with the raw card identifying to the decode chip the failing address information (via solder jumpers). The logic device is an ASIC or programmable logic device which contains the bit steering logic and timing generation logic to redirect defective RAM addresses to an alternate storage device for all read and write operations. The volatile storage device is a RAM array that is used to replace failing address locations in the original reduced specification memory. This array may be in the form a static random access memory (SRAM or DRAM) array, resident in the logic device described above. The size of the device determines the amount of failing addresses that can be allowed in the reduced specification memory.

公开(公告)号：DE602007008612D1

公开(公告)日：2010-09-30

申请号：DE602007008612

申请日：2007-10-08

Applicant: IBM

Inventor： DELL TIMOTHY JAY ,  GLAISE RENE

IPC: H04L1/00 ,  H04L25/03

公开(公告)号：MY117769A

公开(公告)日：2004-08-30

申请号：MYPI9704802

申请日：1997-10-13

Applicant: IBM

Inventor： DELL TIMOTHY JAY ,  KELLOGG MARK WILLIAM

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

Abstract: REDUCED SPECIFICATION DRAMS ARE USED IN MEMORY ASSEMBLIES IN SUCH A WAY AS TO MAXIMIZE THE USE OF THE GOOD CELLS IN THE REDUCED SPECIFICATION DRAM CHIPS. AN EXTERNAL MEMORY ARRAY IS MAPPED TO REPLACE DEFECTIVE MEMORY LOCATIONS ON A REAL TIME BASIS. THE MAJOR COMPONENTS ARE (1) A NON-VOLATILE STORAGE DEVICE, (2) A LOGIC DEVICE, AND (3) A VOLATILE STORAGE DEVICE. THE NON-VOLATILE STORAGE DEVICE, SUCH AS AN EPROM, EEPROM OR A FLASH MEMORY CHIP, IS USED TO RETAIN ADDRESS INFORMATION FOR ALL MEMORY FAILS ON A GIVEN ASSEMBLY. IN SIMPLER IMPLEMENTATIONS, THE USE OF SPECIFIC COMBINATIONS OF RAM FAILURE TYPES CAN BE USED IN ADDITION TO A LOGIC DECODE CHIP, WITH THE RAW CARD IDENTIFYING TO THE DECODE CHIP THE FAILING ADDRESS INFORMATION (VIA SOLDER JUMPERS). THE LOGIC DEVICE IS AN ASIC OR PROGRAMMABLE LOGIC DEVICE WHICH CONTAINS THE BIT STEERING LOGIC AND TIMING GENERATION LOGIC TO REDIRECT DEFECTIVE RAM ADDRESSES TO AN ALTERNATE STORAGE DEVICE FOR ALL READ AND WRITE OPERATIONS. THE VOLATILE STORAGE DEVICE IS A RAM ARRAY THAT IS USED TO REPLACE FAILING ADDRESS LOCATIONS IN THE ORIGINAL REDUCED SPECIFICATION MEMORY. THIS ARRAY MAY BE IN THE FORM A STATIC RANDOM ACCESS MEMORY (SRAM OR DRAM) ARRAY, RESIDENT IN THE LOGIC DEVICE DESCRIBED ABOVE. THE SIZE OF THE DEVICE DETERMINES THE AMOUNT OF FAILING ADDRESSES THAT CAN BE ALLOWED IN THE REDUCED SPECIFICATION MEMORY.(FIG. 1C)