公开(公告)号：DE2861539D1

公开(公告)日：1982-02-25

申请号：DE2861539

申请日：1978-12-20

Applicant: IBM

Inventor： FENG BAI-CWO ,  FENG GEORGE CHENG-CWO

IPC: G03F7/26 ,  G03C1/74 ,  G03F1/68 ,  G03F7/09 ,  G03F7/095 ,  G03F7/16 ,  H01L21/027 ,  H05K3/06 ,  H05K3/14 ,  G03F7/02 ,  G03F1/00

Abstract: A resist mask comprising two layers of resist, one of which is saturated with a dilutant which does not dissolve the other. In one embodiment, the two layers of resist are applied upon a substrate, the first layer of which is more soluble in a developer. The second layer is said saturated resist and the first layer is non-saturated. This composite is preferaly used to form a relief mask with recessed sidewalls used in lift-off processes.

公开(公告)号：DE69432890T2

公开(公告)日：2004-05-27

申请号：DE69432890

申请日：1994-11-09

Applicant: IBM

Inventor： DELL TIMOTHY JAY ,  FENG GEORGE CHENG-CWO ,  KELLOGG MARK WILLIAM

IPC: G11C11/401 ,  G06F1/10 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G11C5/00 ,  G11C7/22 ,  G11C11/407 ,  H01L25/10 ,  H01L25/18 ,  H05K1/02 ,  H05K1/11

Abstract: A packaging assembly for semiconductor memory modules using synchronous clocking signals distributed to each module within a package. The clock distribution network on the assembly is characterized by including a transmission line termination means, preferably a resistor, coupled immediately adjacent to one of the assembly input pins.

公开(公告)号：DE2860161D1

公开(公告)日：1980-12-18

申请号：DE2860161

申请日：1978-06-02

Applicant: IBM

Inventor： FENG BAI-CWO ,  FENG GEORGE CHENG-CWO

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/31 ,  H01L21/314 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/00 ,  H01L21/82

Abstract: A method of forming extremely small impurity regions within other impurity regions without the need for providing critical masks. In the preferred embodiment this is achieved by forming an undercut band within masking layers atop a substrate to define a first impurity region, such as the base region of a bipolar transistor. After this region is formed by the introduction of impurities, the undercut is filled-in by a chemical vapor deposition process. A blocking mask may then be used for the formation of the second impurity region, in this case the emitter, within the first region. The window of the second region is defined by the filled-in band, thereby insuring a selected distance between the peripheries of said first and second impurity regions. The same mask may also be used to form other self-aligned regions with the first region.

公开(公告)号：DE69432890D1

公开(公告)日：2003-08-07

申请号：DE69432890

申请日：1994-11-09

Applicant: IBM

Inventor： DELL TIMOTHY JAY ,  FENG GEORGE CHENG-CWO ,  KELLOGG MARK WILLIAM

IPC: G11C11/401 ,  G06F1/10 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G11C5/00 ,  G11C7/22 ,  G11C11/407 ,  H01L25/10 ,  H01L25/18 ,  H05K1/02 ,  H05K1/11

Abstract: A packaging assembly for semiconductor memory modules using synchronous clocking signals distributed to each module within a package. The clock distribution network on the assembly is characterized by including a transmission line termination means, preferably a resistor, coupled immediately adjacent to one of the assembly input pins.

公开(公告)号：DE2626738A1

公开(公告)日：1977-01-20

申请号：DE2626738

申请日：1976-06-15

Applicant: IBM

Inventor： FENG BAI-CWO ,  FENG GEORGE CHENG-CWO

IPC: H01L21/76 ,  H01L21/32 ,  H01L21/762

Abstract: In the fabrication of integrated circuits, a method is provided for forming recessed silicon dioxide isolation in which the "bird's beak" problem associated with conventional silicon dioxide-silicon nitride composite masking structures is minimized. A conventional composite mask comprising a bottom layer of silicon dioxide and an upper layer of silicon nitride having a plurality of openings defining the regions in the silicon substrate which are to be thermally oxidized is formed on the substrate. Recesses are then etched in the silicon substrate in registration with the openings in the composite mask. The silicon dioxide layer should be, in effect, over-etched to extend the openings in the silicon dioxide to greater lateral dimensions than the openings in the silicon nitride layer whereby the silicon nitride layer at the periphery of the openings is undercut.