中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.019 seconds)

    SIMM/DIMM MEMORY MODULE
    1.
    发明专利
    SIMM/DIMM MEMORY MODULE 失效

    公开(公告)号：JPH11251538A

    公开(公告)日：1999-09-17

    申请号：JP539399

    申请日：1999-01-12

    Applicant: IBM

    Inventor： TIMOTHY J DILL ,  KELLOGG MARK WILLIAM ,  BRUCE GERALD HAZELZETT

    IPC: H01L27/10 ,  G11C5/00 ,  G11C5/06 ,  G11C8/12 ,  G11C11/401 ,  H05K1/11

    Abstract: PROBLEM TO BE SOLVED: To obtain a module functioning as a DIMM or an SIMM when it is inserted into an old or new computer, respectively, by designing the module to emulate a DIMM or an SIMM, respectively, when it is inserted into a DIMM socket or an SIMM. SOLUTION: A DRAM array 27 and a path gate circuit 28 are mounted on a card 10 being interconnected electrically. When a specified edge on the card is inserted into a counterpart DIMM or SIMM socket mounted on a computer system board by selecting pads 22, 24, the path gate circuit is activated or inactivated selectively through selective bias thereof. Consequently, a module functions as an SIMM or a DIMM, respectively, when it is inserted into an SIMM socket or a DIMM socket.

    METHOD FOR CONTROLLING MEMORY OF COMPUTER SYSTEM, AND COMPUTER SYSTEM
    2.
    发明专利
    METHOD FOR CONTROLLING MEMORY OF COMPUTER SYSTEM, AND COMPUTER SYSTEM 失效

    公开(公告)号：JPH10188554A

    公开(公告)日：1998-07-21

    申请号：JP30702997

    申请日：1997-11-10

    Applicant: IBM

    Inventor： CONNOLLY BRIAN J ,  DELL TIMOTHY JAY ,  HAZELZET BRUCE GERARD ,  KELLOGG MARK WILLIAM

    IPC: G11C11/406 ,  G11C11/401 ,  G11C11/407

    Abstract: PROBLEM TO BE SOLVED: To make both CBR and hidden refreshing executable on a DRAM forming a SIMM or a DIMM, by converting each one system RAS and CAS signal into a plurality of RAS and CAS signals for normal read/write operation on the DRAM. SOLUTION: An ASIC chip 78 converts a SYS-RAS signal into RAS-T or RAS-B signals by a signal of a pin A12 or an SYS-CAS signal to CAS-L or CAS-R signals using an address on a pin A10 separately. A RAS sample latch 90 determines whether the cycle corresponds to CBR or not by a signal from a receiver 80 to perform a CBR refreshing or a normal reading/writing. An RAS address latch 92 and a CAS sample latch 96 determine a hidden refreshing by signals from receivers 82 and 84 and an inverter 94 to execute. This accomplishes both of the CBR and the hidden refreshing on a DRAM.

    Synchronous memory modules and memory systems withselectable clock termination
    3.
    发明专利
    Synchronous memory modules and memory systems withselectable clock termination 未知

    公开(公告)号：SG126691A1

    公开(公告)日：2006-11-29

    申请号：SG200201204

    申请日：2002-02-28

    Applicant: IBM

    Inventor： GRUNDON STEVEN A ,  KELLOGG MARK WILLIAM

    IPC: G11C7/00 ,  H03K17/00

    Abstract: Memory systems and/or memory modules allow selectable clock termination between the clock/clock buffer and components of the memory modules. Memory modules can operate in existing (emerging) memory subsystems, as well as meet the low power/low pin count needs of future memory subsystems, with no required changes to the existing/emerging systems. For 184 Pin Registered DIMMs, power savings equate to greater than 200mw/DIMM, and systems are permitted to connect DIMM clocks in serial, similar to address/control lines, thereby increasing the address/control window as well as system read loop- back timings.

    High bandwidth dram with low operating power modes
    5.
    发明专利
    High bandwidth dram with low operating power modes 未知

    公开(公告)号：SG77255A1

    公开(公告)日：2000-12-19

    申请号：SG1999003392

    申请日：1999-07-15

    Applicant: IBM

    Inventor： BERTIN CLAUDE LOUIS ,  KELLOGG MARK WILLIAM ,  HEDBERG ERIK L ,  DELL TIMOTHY JAY

    IPC: G06F13/16 ,  G06F13/38 ,  H01L21/8242

    Abstract: A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.

    Dynamic redundancy for random access memory assemblies
    6.
    发明专利
    Dynamic redundancy for random access memory assemblies 未知

    公开(公告)号：SG64449A1

    公开(公告)日：1999-04-27

    申请号：SG1997003733

    申请日：1997-10-14

    Applicant: IBM

    Inventor： DELL TIMOTHY JAY ,  KELLOGG MARK WILLIAM

    IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F12/16

    Abstract: Reduced specification DRAMs are used in memory assemblies in such a way as to maximize the use of the good cells in the reduced specification DRAM chips. An external memory array is mapped to replace defective memory locations on a real time basis. The major components are (1) a non-volatile storage device, (2) a logic device, and (3) a volatile storage device. The non-volatile storage device, such as an EPROM, EEPROM, or a flash memory chip, is used to retain address information for all memory fails on a given assembly. In simpler implementations, the use of specific combinations of RAM failure types can be used in addition to a logic decode chip, with the raw card identifying to the decode chip the failing address information (via solder jumpers). The logic device is an ASIC or programmable logic device which contains the bit steering logic and timing generation logic to redirect defective RAM addresses to an alternate storage device for all read and write operations. The volatile storage device is a RAM array that is used to replace failing address locations in the original reduced specification memory. This array may be in the form a static random access memory (SRAM or DRAM) array, resident in the logic device described above. The size of the device determines the amount of failing addresses that can be allowed in the reduced specification memory.

    DYNAMIC REDUNDANCY FOR RANDOM ACCESS MEMORY ASSEMBLIES
    7.
    发明专利
    DYNAMIC REDUNDANCY FOR RANDOM ACCESS MEMORY ASSEMBLIES 未知

    公开(公告)号：MY117769A

    公开(公告)日：2004-08-30

    申请号：MYPI9704802

    申请日：1997-10-13

    Applicant: IBM

    Inventor： DELL TIMOTHY JAY ,  KELLOGG MARK WILLIAM

    IPC: G01R31/28 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

    Abstract: REDUCED SPECIFICATION DRAMS ARE USED IN MEMORY ASSEMBLIES IN SUCH A WAY AS TO MAXIMIZE THE USE OF THE GOOD CELLS IN THE REDUCED SPECIFICATION DRAM CHIPS. AN EXTERNAL MEMORY ARRAY IS MAPPED TO REPLACE DEFECTIVE MEMORY LOCATIONS ON A REAL TIME BASIS. THE MAJOR COMPONENTS ARE (1) A NON-VOLATILE STORAGE DEVICE, (2) A LOGIC DEVICE, AND (3) A VOLATILE STORAGE DEVICE. THE NON-VOLATILE STORAGE DEVICE, SUCH AS AN EPROM, EEPROM OR A FLASH MEMORY CHIP, IS USED TO RETAIN ADDRESS INFORMATION FOR ALL MEMORY FAILS ON A GIVEN ASSEMBLY. IN SIMPLER IMPLEMENTATIONS, THE USE OF SPECIFIC COMBINATIONS OF RAM FAILURE TYPES CAN BE USED IN ADDITION TO A LOGIC DECODE CHIP, WITH THE RAW CARD IDENTIFYING TO THE DECODE CHIP THE FAILING ADDRESS INFORMATION (VIA SOLDER JUMPERS). THE LOGIC DEVICE IS AN ASIC OR PROGRAMMABLE LOGIC DEVICE WHICH CONTAINS THE BIT STEERING LOGIC AND TIMING GENERATION LOGIC TO REDIRECT DEFECTIVE RAM ADDRESSES TO AN ALTERNATE STORAGE DEVICE FOR ALL READ AND WRITE OPERATIONS. THE VOLATILE STORAGE DEVICE IS A RAM ARRAY THAT IS USED TO REPLACE FAILING ADDRESS LOCATIONS IN THE ORIGINAL REDUCED SPECIFICATION MEMORY. THIS ARRAY MAY BE IN THE FORM A STATIC RANDOM ACCESS MEMORY (SRAM OR DRAM) ARRAY, RESIDENT IN THE LOGIC DEVICE DESCRIBED ABOVE. THE SIZE OF THE DEVICE DETERMINES THE AMOUNT OF FAILING ADDRESSES THAT CAN BE ALLOWED IN THE REDUCED SPECIFICATION MEMORY.(FIG. 1C)

Patent Agency Ranking