公开(公告)号：JP2005168029A

公开(公告)日：2005-06-23

申请号：JP2004349506

申请日：2004-12-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FENG KAI D ,  WU HONGFEI

IPC: H03K5/14 ,  G01R1/00 ,  H03H11/26 ,  H03K5/00 ,  H03K5/06 ,  H03K5/13 ,  H03K5/1532 ,  H03K17/693 ,  H03K19/0948 ,  H03K19/173

CPC classification number: H03K5/06 ,  H03K5/13 ,  H03K2005/00058 ,  H03K2005/00293

Abstract: PROBLEM TO BE SOLVED: To provide a delay unit capable of shortening a delay time to a picoseconds (ps) range.
SOLUTION: A method and a device program a dual edge programmable delay unit that responds to an input signal with a a rise time and a fall time, includes a buffer which receives the input signal and provides an output signal with programmed variable delays between the rise and fall times of the output signal. Programmable control sources (PCS) provide separate control inputs to a buffer. The FTPCS charges a capacitor in the buffer when the input signal changes from high to low to adjust a time delay before the fall of the buffer output signal. The RTPCS discharges the capacitor in the buffer when the input signal changes from low to high to adjust the time delay before the rise of the buffer output signal.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种能够将延迟时间缩短到皮秒（ps）范围的延迟单元。 解决方案：一种在上升时间和下降时间响应输入信号的双边缘可编程延迟单元的方法和设备程序包括缓冲器，其接收输入信号并提供输出信号，其中编程的可变延迟在 输出信号的上升和下降时间。 可编程控制源（PCS）为缓冲区提供单独的控制输入。 当输入信号从高电平变为低电平时，FTPCS在缓冲器中为电容器充电，以在缓冲器输出信号下降之前调整时间延迟。 当输入信号从低电平变为高电平时，RTPCS将缓冲器中的电容放电，以调整缓冲器输出信号上升之前的时间延迟。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2011040725A

公开(公告)日：2011-02-24

申请号：JP2010158143

申请日：2010-07-12

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FEN CHEN ,  FENG KAI D ,  HE ZHONG-XIANG

IPC: H01L21/8234 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092

CPC classification number: G01R31/2621 ,  G01R31/2855 ,  G01R31/2894

Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit system for assessing reliability of an integrated circuit having many field-effect-transistors. SOLUTION: This invention provides the method. The method includes: operating a plurality of field-effect-transistors (FETs) under a first operation condition; reversing an operation direction for at least one of the plurality of FETs for a brief period of time; measuring a second operation condition of the one of the plurality of FETs during the brief period of time; computing a difference between the second operation condition and a reference operation condition; and providing a reliability indicator based upon the difference between the second and the reference operation conditions, wherein the plurality of FETs are employed in a single integrated circuit (IC). COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于评估具有许多场效应晶体管的集成电路的可靠性的方法和电路系统。 解决方案：本发明提供了该方法。 该方法包括：在第一操作条件下操作多个场效应晶体管（FET）; 短时间内反转多个FET中的至少一个的操作方向; 在短时间内测量所述多个FET中的一个的第二操作条件; 计算第二操作条件和参考操作条件之间的差; 以及基于所述第二参考操作条件和所述参考操作条件之间的差异提供可靠性指示器，其中所述多个FET用于单个集成电路（IC）。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2006013111A

公开(公告)日：2006-01-12

申请号：JP2004187571

申请日：2004-06-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DING HANYI ,  FENG KAI D ,  HE ZHONG-XIANG ,  LIU XUEFENG

IPC: H01F17/04 ,  H01F27/28 ,  H01F27/42 ,  H01F37/00 ,  H01F41/04

Abstract: PROBLEM TO BE SOLVED: To provide an inductor being formed on an integrated circuit chip.
SOLUTION: The on-chip inductor comprises one or a plurality of inner layers (12) existing between two or more outer layers (14), an inductor metal wiring turn (16) included in the one or a plurality of inner layers (12), and a magnetic member for forming the two or more outer layers (14) and the one or a plurality of inner layers (12). In one embodiment, the magnetic member is photoresist paste containing magnetic particles. In another embodiment, the magnetic member is a series of magnetic metal strips (32 and 36) arranged, respectively, on the first and second parts (30 and 34) of the two or more outer layers (14) and on the one or a plurality of inner layers (12), respectively. The series of magnetic metal strips on the first and second parts (30 and 34) form a lattice pattern. Other mode includes deposition of a compound controlled adjustably and a control winding having an adjustable current.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供形成在集成电路芯片上的电感器。 片上电感器包括存在于两个或多个外层（14）之间的一个或多个内层（12），包含在一个或多个内层（14）中的电感器金属布线匝（16） （12），以及用于形成所述两个或更多个外层（14）和所述一个或多个内层（12）的磁性构件。 在一个实施例中，磁性构件是含有磁性颗粒的光致抗蚀剂浆料。 在另一个实施例中，磁性构件是分别布置在两个或多个外层（14）的第一和第二部分（30和34）上并且在一个或多个外层（14）上的一系列磁性金属条（32和36） 多个内层（12）。 第一和第二部分（30和34）上的一系列磁性金属条形成格子图案。 其他模式包括可调整控制的化合物的沉积和具有可调电流的控制绕组。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：CA2311435C

公开(公告)日：2004-04-20

申请号：CA2311435

申请日：2000-06-13

Applicant: IBM CANADA

Inventor： FENG KAI D

IPC: H04B10/50 ,  H01S5/042 ,  H04B10/04 ,  H04B10/14

Abstract: A high efficiency LED driver circuit utilizing a capacitor to regulate the L ED driving current. The voltage across the capacitor is monitored to maintain a preselected low threshold voltage on the capacitor, which determines the LED optical emission intensity. The capacito r provides the LED driver current by discharging through the LED during transmission intervals, and the power supply for the device is used only to maintain the capacitor charge level. The LED driver circuit of the invention accordingly operates at high efficiency with low power consumption . The LED driver current can be regulated by changing the low and high threshold voltages of the capacitor pump controller, to thus control the optical intensity of the LED.

公开(公告)号：GB2524429A

公开(公告)日：2015-09-23

申请号：GB201511989

申请日：2014-01-07

Applicant: IBM

Inventor： FENG KAI D ,  WANG PING-CHUAN ,  YANG ZHIJIAN ,  YASHCHIN EMMANUEL

IPC: H03B29/00 ,  G06F7/58

Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safeguard the zener diode from catastrophic burn-out.

公开(公告)号：DE112012004202T5

公开(公告)日：2014-07-03

申请号：DE112012004202

申请日：2012-10-24

Applicant: IBM

Inventor： YANG ZHIJIAN ,  WANG PING-CHUAN ,  FENG KAI D ,  HOSTETTER JUN EDWIN J

IPC: H03K17/30 ,  H03K17/687

Abstract: Ein Verfahren und eine Vorrichtung zum Instandsetzen von Transistoren weisen das Anlegen einer ersten Spannung an eine Source eines PFET, einer zweiten Spannung an das Gate eines PFET und einer dritten Spannung an den Drain eines PFET über eine vorbestimmte Zeit auf. Wobei die erste Spannung größer als die zweite Spannung und die zweite Spannung größer als die dritte Spannung ist. Durch Anlegen dieser Spannungen stellten die Erfinder fest, dass die Löcher, die im Gate-Dielektrikum eingeschlossen sind, vermindert werden. Auf diese Weise kann die Halbleiterstruktur instandgesetzt bzw. auf oder annähernd auf die ursprünglichen Betriebseigenschaften zurückgestellt werden. Eine zusätzliche Ausführungsform ist ein Verfahren und eine Vorrichtung zum Instandsetzen eines NFET-Transistors durch Anlegen einer ersten Spannung an einen Drain eines NFET, einer zweiten Spannung an das Gate des NFET und einer dritten Spannung an die Source eines NFET über eine vorbestimmte Zeit. Die erste Spannung ist größer als die zweite Spannung und die zweite Spannung größer als die dritte Spannung. Wie bei der ersten Ausführungsform veranschaulicht, liegt das Ziel der Erfindung darin, den Transistor instandzusetzen. Im Falle des NFET sammeln sich die Elektronen während des normalen Betriebs auf dem Gate-Dielektrikum an. Durch Anlegen der Spannungen in der beschriebenen Weise kann der Transistor instandgesetzt werden, so dass er mit oder nahe den ursprünglichen Spezifikationen betrieben wird.

公开(公告)号：CA2311433C

公开(公告)日：2004-12-28

申请号：CA2311433

申请日：2000-06-13

Applicant: IBM CANADA

Inventor： FENG KAI D

IPC: H04B10/69 ,  H04B10/06 ,  H04B10/14

Abstract: An optical receiver circuit comprising a plurality of PIN diodes, each associated with a dedicated element transimpedance amplifier, the outputs of the element transimpedance amplifiers being connected to a summing amplifier which sums the voltages output from t he element transimpedance amplifiers. The circuit of the invention provides the same output voltage value as a single large PIN diode having an active area comparable to the sum of the active areas of the smaller PIN diodes, and thus has the same high sensitivity as the single lar ge PIN diode but a much wider bandwidth.

公开(公告)号：CA2312516C

公开(公告)日：2004-03-02

申请号：CA2312516

申请日：2000-06-27

Applicant: IBM CANADA

Inventor： FENG KAI D

IPC: H04B10/40 ,  H04B10/14

Abstract: An IR transceiver having a receiver chain with an isolated analog output, provides a transmission gate and unity gain buffer interposed between the amplifier output and an analog output pad. The transmission gate behaves as a switch, passing the analog output signal to the analog output pad only when an analog output is required. The unity gain buffer has a high input resistance, a low input capacitance, a unit gain and a low output impedance, so that the load of a DSP device or measuring instrument on the analog output pad is isolated and does not affec t the performance of the receiver chain. Since the transfer rates of the transmission gate and the buffer are each a unity, the analog output pad provides a high fidelity analog output signal to the outpu t buffer.

公开(公告)号：CA2311434A1

公开(公告)日：2001-12-13

申请号：CA2311434

申请日：2000-06-13

Applicant: IBM CANADA

Inventor： HARTLEY LEE F ,  FENG KAI D

IPC: H03F3/08 ,  H03K17/785 ,  H04B10/06 ,  H04B10/14

Abstract: A photoelectric receiver circuit provides a symmetrical sensor having a transimpedance amplifier on each side of the PIN diode, the outputs of the transimpedance amplifiers being AC coupled to a differential post amplifier. The differential structure provide s a very high common noise voltage rejection ratio and a virtual ground to the inverting inputs of the transimpedance amplifiers. In the preferred embodiment a differential PIN diode bias voltage is established by separate bias voltages respectively applied to the non-inverting input of each transimpedance amplifier. Thus, a low-noise voltage regulator can be used to supply power to the bias voltages in the invention, and the AC coupling capacitors can be very small to conserve space on the chip die. Auxiliary DC currents applied to both sides of the PIN diode maintain the PIN diode bias as high as possible and maximize the output swing ranges of the transimpedance amplifiers in order t o retain a wide bandwidth. The DC current sources allow the output bias voltages of the transimpedance amplifiers to be adjusted, and when controlled by the transimpedance amplifier outputs through a low pass filter, the output bias offset caused by ambient light can be eliminated. Th e feedback resistors may be variable resistors to provide automatic gain control.

公开(公告)号：DE112014000289T5

公开(公告)日：2015-12-03

申请号：DE112014000289

申请日：2014-01-07

Applicant: IBM

Inventor： FENG KAI D ,  WANG PING-CHUAN ,  YANG ZHIJIAN ,  YASHCHIN EMMANUEL

IPC: G06F7/58 ,  G06F21/71 ,  G06F21/73

Abstract: Ein echter Rauschgenerator auf einem Chip, der eine eingebettete Rauschquelle mit einer (bzw. mehreren) Zenerdiode(n) mit niedriger Spannung und hohem Rauschen sowie eine lokale Regelschleifen-Zenerdioden-Stromsteuerschaltung enthält. Die vorliegende Erfindung schlägt die Verwendung von stark dotierten Polysilicium- und Silicium-p-n-Diodenstrukturen zum Minimieren der Durchbruchspannung, Erhöhen des Rauschpegels und Verbessern der Zuverlässigkeit vor. Die vorlegende Erfindung schlägt auch eine lokale Regelschleifen-Zenerdioden-Steuerschaltung zum Schützen der Zenerdiode vor einer totalen Überlastung vor.