公开(公告)号：DE2336908A1

公开(公告)日：1974-05-09

申请号：DE2336908

申请日：1973-07-20

Applicant: IBM

Inventor： CALHOUN HARRY CHARLES ,  FREED LARRY ERNEST ,  KAUFMAN CARL LEE

IPC: H01L21/00 ,  H01L23/485 ,  H01L23/522 ,  H01L1/14

公开(公告)号：DE2364787A1

公开(公告)日：1974-07-11

申请号：DE2364787

申请日：1973-12-27

Applicant: IBM

Inventor： FREED LARRY ERNEST ,  NESTORK WILLIAM JOHN ,  TUMAN DANIEL

IPC: G01R31/28 ,  H01L23/544 ,  H01L27/07 ,  H01L19/00

Abstract: In integrated semiconductor circuits comprising a plurality of active and passive devices interconnected by conductive means into a selected circuit configuration, the improvement wherein said circuit configuration is arranged so as to be free of possible paths displaying reactance which would be alternative to selected substantially reactanceless paths terminating in critical circuit nodes in the event of structural failure of one of said reactanceless paths, whereby the DC testing of the integrated circuit is not affected by such alternative paths.

公开(公告)号：DE2313725A1

公开(公告)日：1973-10-11

申请号：DE2313725

申请日：1973-03-20

Applicant: IBM

Inventor： BATTISTA MARIO ALPHONSE ,  FREED LARRY ERNEST ,  HARBISON RICHARD STEPHEN ,  NESTORK WILLIAM JOHN ,  STRUK JAMES ROBERT ,  TUMAN DANIEL

IPC: H01L21/822 ,  H01L21/761 ,  H01L21/82 ,  H01L23/485 ,  H01L27/00 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118 ,  H01L19/00