公开(公告)号：DE2313725A1

公开(公告)日：1973-10-11

申请号：DE2313725

申请日：1973-03-20

Applicant: IBM

Inventor： BATTISTA MARIO ALPHONSE ,  FREED LARRY ERNEST ,  HARBISON RICHARD STEPHEN ,  NESTORK WILLIAM JOHN ,  STRUK JAMES ROBERT ,  TUMAN DANIEL

IPC: H01L21/822 ,  H01L21/761 ,  H01L21/82 ,  H01L23/485 ,  H01L27/00 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118 ,  H01L19/00

公开(公告)号：DE2615758A1

公开(公告)日：1977-01-20

申请号：DE2615758

申请日：1976-04-10

Applicant: IBM

Inventor： NESTORK WILLIAM JOHN ,  PARISI JOHN ANTHONY

IPC: H01L23/14 ,  H01L23/538 ,  H01L25/065 ,  H05K3/36

公开(公告)号：DE2612667A1

公开(公告)日：1976-10-28

申请号：DE2612667

申请日：1976-03-25

Applicant: IBM

Inventor： MAGDO INGRID EMESE ,  MAGDO STEVEN ,  NESTORK WILLIAM JOHN

IPC: H01L27/00 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L23/535

Abstract: A process for forming complete dielectrically isolated monocrystalline silicon regions on a substrate by depositing a first epitaxial silicon layer embodying an N-type impurity on a low resistivity silicon substrate embodying a P-type impurity, forming annular P-type impurity regions in the first epitaxial layer, depositing the second epitaxial layer embodying an N-type impurity on the first epitaxial layer, forming annular P-type impurity regions in the second epitaxial layer in registry with the annular regions in the first epitaxial layer, converting the silicon substrate and the annular P-type regions in the first and second epitaxial layers into porous silicon material by an anodic treatment carried out in an aqueous solution of hydrofluoric acid, and oxidizing the porous silicon material to form silicon oxide.

公开(公告)号：DE3277890D1

公开(公告)日：1988-02-04

申请号：DE3277890

申请日：1982-07-16

Applicant: IBM

Inventor： DOUGHERTY WILLIAM EDWIN ,  GREER STUART EUGENE ,  NESTORK WILLIAM JOHN ,  NORRIS WILLIAM TILDEN

IPC: H01L23/52 ,  H01L23/538

公开(公告)号：DE2364787A1

公开(公告)日：1974-07-11

申请号：DE2364787

申请日：1973-12-27

Applicant: IBM

Inventor： FREED LARRY ERNEST ,  NESTORK WILLIAM JOHN ,  TUMAN DANIEL

IPC: G01R31/28 ,  H01L23/544 ,  H01L27/07 ,  H01L19/00

Abstract: In integrated semiconductor circuits comprising a plurality of active and passive devices interconnected by conductive means into a selected circuit configuration, the improvement wherein said circuit configuration is arranged so as to be free of possible paths displaying reactance which would be alternative to selected substantially reactanceless paths terminating in critical circuit nodes in the event of structural failure of one of said reactanceless paths, whereby the DC testing of the integrated circuit is not affected by such alternative paths.

公开(公告)号：DE3887849T2

公开(公告)日：1994-08-11

申请号：DE3887849

申请日：1988-11-22

Applicant: IBM

Inventor： DIETSCH HANS ERICH ,  NESTORK WILLIAM JOHN

IPC: H01L21/60 ,  H01L21/00 ,  H01L23/32 ,  H01L23/50 ,  H01L23/42

公开(公告)号：DE3887849D1

公开(公告)日：1994-03-24

申请号：DE3887849

申请日：1988-11-22

Applicant: IBM

Inventor： DIETSCH HANS ERICH ,  NESTORK WILLIAM JOHN

IPC: H01L21/60 ,  H01L21/00 ,  H01L23/32 ,  H01L23/50 ,  H01L23/42

公开(公告)号：DE2258483A1

公开(公告)日：1973-07-05

申请号：DE2258483

申请日：1972-11-29

Applicant: IBM

Inventor： NESTORK WILLIAM JOHN

IPC: H01L21/822 ,  H01L21/82 ,  H01L23/31 ,  H01L23/535 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118 ,  H01L1/14

Abstract: A semiconductor integrated circuit masterslice comprising semiconductor substrate having a center of origin and arcuate or annular conductive lines thereon. A plurality of cell groups are symmetrically located on the semiconductor substrate with respect to radial lines extending from the center of origin so as to significantly increase packing densities compared to that available with orthongonally or randomly disposed monolithic integrated circuit structures.