公开(公告)号：DE69022025D1

公开(公告)日：1995-10-05

申请号：DE69022025

申请日：1990-03-13

Applicant: IBM

Inventor： BARUCCHI GERARD ,  GALCERA JOSE ,  TOUBOL GILLES ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

IPC: G06F1/12 ,  H03L7/06 ,  H04J3/06 ,  H04L7/00

Abstract: The synchronization circuit resynchronizes the data bits received from remote devices from line or link 20-1 with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in a n-bit cyclic buffer (114-1) with the received bit clock CS and they are sequentially picked at the opposite buffer position with the central clock CO The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.

公开(公告)号：DE69022025T2

公开(公告)日：1996-04-18

申请号：DE69022025

申请日：1990-03-13

Applicant: IBM

Inventor： BARUCCHI GERARD ,  GALCERA JOSE ,  TOUBOL GILLES ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

IPC: G06F1/12 ,  H03L7/06 ,  H04J3/06 ,  H04L7/00

Abstract: The synchronization circuit resynchronizes the data bits received from remote devices from line or link 20-1 with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in a n-bit cyclic buffer (114-1) with the received bit clock CS and they are sequentially picked at the opposite buffer position with the central clock CO The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.