公开(公告)号：DE69022025D1

公开(公告)日：1995-10-05

申请号：DE69022025

申请日：1990-03-13

Applicant: IBM

Inventor： BARUCCHI GERARD ,  GALCERA JOSE ,  TOUBOL GILLES ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

IPC: G06F1/12 ,  H03L7/06 ,  H04J3/06 ,  H04L7/00

Abstract: The synchronization circuit resynchronizes the data bits received from remote devices from line or link 20-1 with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in a n-bit cyclic buffer (114-1) with the received bit clock CS and they are sequentially picked at the opposite buffer position with the central clock CO The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.

公开(公告)号：DE68916413D1

公开(公告)日：1994-07-28

申请号：DE68916413

申请日：1989-03-14

Applicant: IBM

Inventor： BARUCCHI GERARD ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

IPC: G06F15/16 ,  G06F15/167 ,  G06F15/173

Abstract: The system performs an optimized number of simultaneous transfers of data packets between pairs of units comprising an origin unit and a target unit selected among N data processing units (8). Each data processing unit comprises a set of outbound queues with one outbound queue associated with each one of the data processing units to which it may send data packets, for storing the data packets to be sent by the data processing unit to the data processing unit associated with said one outbound queue. The transfers are performed during a time burst Ti+1 by data switch 6 under control of switching control signals sent to data switch by the units on lines 16-1 to 16-N in response to control out signals generated by scheduler 4 during previous burst time Ti. The scheduler runs a selection algorithm which gives each unit an equal probability to be selected as origin unit in a given period.

公开(公告)号：FR2406916A1

公开(公告)日：1979-05-18

申请号：FR7732158

申请日：1977-10-18

Applicant: IBM FRANCE

Inventor： GERGAUD CLAUDE ,  GRIMANELLI ETIENNE ,  TRACOL ANDRE

IPC: G06F13/00 ,  H04L12/403 ,  H04L12/423 ,  H04L11/20

公开(公告)号：DE69022025T2

公开(公告)日：1996-04-18

申请号：DE69022025

申请日：1990-03-13

Applicant: IBM

Inventor： BARUCCHI GERARD ,  GALCERA JOSE ,  TOUBOL GILLES ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

IPC: G06F1/12 ,  H03L7/06 ,  H04J3/06 ,  H04L7/00

Abstract: The synchronization circuit resynchronizes the data bits received from remote devices from line or link 20-1 with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in a n-bit cyclic buffer (114-1) with the received bit clock CS and they are sequentially picked at the opposite buffer position with the central clock CO The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.

公开(公告)号：DE68916413T2

公开(公告)日：1995-01-26

申请号：DE68916413

申请日：1989-03-14

Applicant: IBM

Inventor： BARUCCHI GERARD ,  CALVIGNAC JEAN ,  ORSATTI DANIEL ,  TRACOL ANDRE

IPC: G06F15/16 ,  G06F15/167 ,  G06F15/173

Abstract: The system performs an optimized number of simultaneous transfers of data packets between pairs of units comprising an origin unit and a target unit selected among N data processing units (8). Each data processing unit comprises a set of outbound queues with one outbound queue associated with each one of the data processing units to which it may send data packets, for storing the data packets to be sent by the data processing unit to the data processing unit associated with said one outbound queue. The transfers are performed during a time burst Ti+1 by data switch 6 under control of switching control signals sent to data switch by the units on lines 16-1 to 16-N in response to control out signals generated by scheduler 4 during previous burst time Ti. The scheduler runs a selection algorithm which gives each unit an equal probability to be selected as origin unit in a given period.