公开(公告)号：JP2011022993A

公开(公告)日：2011-02-03

申请号：JP2010109001

申请日：2010-05-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GAO YAOQING ,  SILVERA RAUL ESTEBAN ,  ARCHAMBAULT ROCH GEORGES ,  GRAHAM YIN ,  MARK PETER MENDELL ,  MARTIN ALLAN RUSSELL

IPC: G06F9/45

CPC classification number: G06F8/4442 ,  G06F11/3466 ,  G06F11/3624 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2201/885

Abstract: PROBLEM TO BE SOLVED: To optimize execution of an application in a compiler.
SOLUTION: In a method for making a computer execute, a plurality of code regions of an application are instrumented with annotations for generating profile data (S410), the execution of the application instrumented with code regions generates profile data for each of the plurality of code regions (S420), a delinquent code region is identified on the basis of the profile data (S430), a plurality of code partial regions of the delinquent code region are instrumented with annotations for generating profile data (S440), the execution of the application having the instrumented code partial regions generates profile data (S450), the delinquent code partial region is identified on the basis of the generated profile data (S460), and application execution is optimized by using the delinquent code partial region (S470).
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：优化编译器中应用程序的执行。 解决方案：在一种用于使计算机执行的方法中，应用程序的多个代码区域具有用于生成简档数据的注释（S410），用代码区域检测的应用程序的执行生成用于 多个代码区域（S420），基于简档数据来识别违规代码区域（S430），对代码区域的多个代码部分区域进行了用于生成简档数据的注释（S440），执行 （S450），根据生成的简档数据识别违法代码部分区域（S460），通过使用违规代码部分区域来优化应用程序执行（S470） 。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：CA2672337C

公开(公告)日：2017-01-03

申请号：CA2672337

申请日：2009-07-15

Applicant: IBM CANADA LTD - IBM CANADA LIMITEE

Inventor： GAO YAOQING ,  SILVERA RAUL ESTEBAN ,  ARCHAMBAULT ROCH GEORGES ,  YIU GRAHAM ,  MENDELL MARK PETER ,  MARTIN ALLAN RUSSELL

IPC: G06F9/45

Abstract: Systems, methods and articles of manufacture are disclosed for optimizing execution of an application. A plurality of code regions of the application may be instrumented with annotations for generating profile data for each of the plurality of code regions. Profile data for each of the plurality of code regions may be generated via executing the application having instrumented code regions. A delinquent code region may be identified based on the generated profile data for each of the plurality of code regions. A plurality of code sub-regions of the identified delinquent code region may be instrumented with annotations for generating profile data for each of the plurality of code sub-regions. Profile data for each of the plurality of code sub-regions may be generated via executing the application having instrumented code sub-regions. A delinquent code sub-region may be identified based on the generated profile data for each of the plurality of code sub-regions. Execution of the application may be optimized using the identified delinquent code sub-region.

公开(公告)号：CA2680597A1

公开(公告)日：2009-12-23

申请号：CA2680597

申请日：2009-10-16

Applicant: IBM CANADA

Inventor： ARCHAMBAULT ROCH G ,  CHEN TONG ,  GAO YAOQING ,  SURA ZEHRA ,  SILVERA RAUL E ,  MOHAMMED KHALED ,  PEKHIMENKO GENNADY ,  O'BRIEN JOHN K

IPC: G06F9/44 ,  G06F9/46

Abstract: An illustrative embodiment provides a computer-implemented process for managing speculative assist threads for data pre-fetching that analyzes collected source code and cache profiling information to identify a code region containing a delinquent load instruction and generates an assist thread, including a value for a local version number, at a program entry point within the identified code region. Upon activation of the assist thread the local version number of the assist thread is compared to the global unique version number of the main thread for the identified code region and an iteration distance between the assist thread relative to the main thread is compared to a predefined value. The assist thread is executed when the local version number of the assist thread matches the global unique version number of the main thread, and the iteration distance between the assist thread relative to the main thread is within a predefined range of values.

公开(公告)号：CA2830605A1

公开(公告)日：2015-04-22

申请号：CA2830605

申请日：2013-10-22

Applicant: IBM CANADA

Inventor： WANG KAI-TING AMY ,  GAO YAOQING ,  BOETTIGER HANS ,  OHMACHT MARTIN

IPC: G06F9/44

Abstract: An illustrative embodiment of a computer-implemented process for a computer-implemented process for code versioning for enabling transactional memory region promotion receives a portion of candidate source code and outlines the portion of candidate source code received for parallel execution. The computer-implemented process further wraps a critical region with entry and exit routines to enter into a speculation sub-process, wherein the entry and exit routines also gather conflict statistics at runtime. The outlined code portion is executed to determine to use a particular one of multiple loop versions according to the conflict statistics gathered at run time.

公开(公告)号：CA2672337A1

公开(公告)日：2011-01-15

申请号：CA2672337

申请日：2009-07-15

Applicant: IBM CANADA

Inventor： GAO YAOQING ,  SILVERA RAUL ESTEBAN ,  ARCHAMBAULT ROCH GEORGES ,  YIU GRAHAM ,  MENDELL MARK PETER ,  MARTIN ALLAN RUSSELL

IPC: G06F9/45

公开(公告)号：CA2680601A1

公开(公告)日：2009-12-23

申请号：CA2680601

申请日：2009-10-16

Applicant: IBM CANADA

Inventor： CHEN TONG ,  GAO YAOQING

IPC: G06F12/02 ,  G06F12/0862 ,  G06F9/46 ,  G06F12/0811

Abstract: An illustrative embodiment provides a computer-implemented process for managing multiple speculative assist threads for data pre-fetching that sends a comma nd from an assist thread of a first processor to second processor and a memory, wherein parameters of the command specify a processor identifier of the second processor, responsive t o receiving the command, reply by the second processor indicating an ability to receive a cache line that is a target of a pre-fetch, responsive to receiving the command replying by the memory indicating a capability to provide the cache line, responsive to receiving replies from t he second processor and the memory, sending, by the first processor, a combined response to the second processor and the memory, wherein the combined response indicates an action, and responsive to the action indicating a transaction can continue sending the requested cache line, by t he memory, to the second processor into a target cache level on the second processor.

公开(公告)号：CA2503263A1

公开(公告)日：2005-10-30

申请号：CA2503263

申请日：2005-04-19

Applicant: IBM

Inventor： BLAINEY ROBERT JAMES ,  ARCHAMBAULT ROCH GEORGES ,  GAO YAOQING

IPC: G06F9/45

Abstract: A compiling program with cache utilization optimizations employs an inter- procedural global analysis of the data access patterns of compile units to be processed . The global analysis determines sufficient information to allow intelligent application of optimization techniques to be employed to enhance the operation and utilization of the available cache systems on target hardware.

公开(公告)号：CA2684441C

公开(公告)日：2012-06-05

申请号：CA2684441

申请日：2009-09-22

Applicant: IBM CANADA

Inventor： ARCHAMBAULT ROCH G ,  CUI SHIMIN ,  GAO YAOQING

IPC: G06F9/44

Abstract: An illustrative embodiment provides a computer-implemented process for may--constant propagation, obtains a source code, and generates a set of associated data structures from the source code and a set of may-constant data structures. The computer--implemented process identifies a candidate code for may-constant propagation to form an identified candidate code, updates the set of may-constant data structures, and selects an identified candidate code using information in the may-constant data structures, including probability, to form a selected candidate code. The computer-implemented process further identifies a code region associated with the selected candidate code to form an identified code region and modifies the identified code region including the selected candidate code.

公开(公告)号：CA2680597C

公开(公告)日：2011-06-07

申请号：CA2680597

申请日：2009-10-16

Applicant: IBM CANADA

Inventor： ARCHAMBAULT ROCH G ,  CHEN TONG ,  GAO YAOQING ,  MOHAMMED KHALED ,  O'BRIEN JOHN K ,  PEKHIMENKO GENNADY ,  SILVERA RAUL E ,  SURA ZEHRA

IPC: G06F9/44 ,  G06F9/46

Abstract: An illustrative embodiment provides a computer-implemented process for managing speculative assist threads for data pre-fetching that analyzes collected source code and cache profiling information to identify a code region containing a delinquent load instruction and generates an assist thread, including a value for a local version number, at a program entry point within the identified code region. Upon activation of the assist thread the local version number of the assist thread is compared to the global unique version number of the main thread for the identified code region and an iteration distance between the assist thread relative to the main thread is compared to a predefined value. The assist thread is executed when the local version number of the assist thread matches the global unique version number of the main thread, and the iteration distance between the assist thread relative to the main thread is within a predefined range of values.

公开(公告)号：CA2680601C

公开(公告)日：2010-11-02

申请号：CA2680601

申请日：2009-10-16

Applicant: IBM CANADA

Inventor： CHEN TONG ,  GAO YAOQING

IPC: G06F12/02 ,  G06F12/0862 ,  G06F9/46 ,  G06F12/0811

Abstract: An illustrative embodiment provides a computer-implemented process for managing multiple speculative assist threads for data pre-fetching that sends a command from an assist thread of a first processor to second processor and a memory, wherein parameters of the command specify a processor identifier of the second processor, responsive to receiving the command, reply by the second processor indicating an ability to receive a cache line that is a target of a pre-fetch, responsive to receiving the command replying by the memory indicating a capability to provide the cache line, responsive to receiving replies from the second processor and the memory, sending, by the first processor, a combined response to the second processor and the memory, wherein the combined response indicates an action, and responsive to the action indicating a transaction can continue sending the requested cache line, by the memory, to the second processor into a target cache level on the second processor.