公开(公告)号：DE3485457D1

公开(公告)日：1992-02-27

申请号：DE3485457

申请日：1984-11-14

Applicant: IBM

Inventor： ANANTHA NARASIPUR G ,  GAUR SANTOSH P ,  HUANG YI-SHIOU ,  TSANG PAUL J

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8224 ,  H01L29/08 ,  H01L29/735 ,  H01L21/00 ,  H01L21/82

Abstract: A method for making a lateral PNP transistor (simultaneously with an NPN transistor) and the resultant device wherein a first mask (76) defines a base-width by the resistor implant (78, 80) for a P-type resistor and a second mask (86) is overlaid asymmetricially on said first mask to partially cover the collector (80). At the same time that the NPN extrinsic base contact is made, P-type dopants-are introduced in the areas (88, 89) exposed by the first and second masks to provide an emitter (92) and a collector contact (94) for the PNP transistor, said transistor thus featuring a graded collector (96, 94) with a high punch-through voltage.