2.
    发明专利
    未知

    公开(公告)号:DE3485457D1

    公开(公告)日:1992-02-27

    申请号:DE3485457

    申请日:1984-11-14

    Applicant: IBM

    Abstract: A method for making a lateral PNP transistor (simultaneously with an NPN transistor) and the resultant device wherein a first mask (76) defines a base-width by the resistor implant (78, 80) for a P-type resistor and a second mask (86) is overlaid asymmetricially on said first mask to partially cover the collector (80). At the same time that the NPN extrinsic base contact is made, P-type dopants-are introduced in the areas (88, 89) exposed by the first and second masks to provide an emitter (92) and a collector contact (94) for the PNP transistor, said transistor thus featuring a graded collector (96, 94) with a high punch-through voltage.

    METHOD FOR FORMING RECESSED REGIONS OF THERMALLY OXIDIZED SILICON AND STRUCTURES THEREOF

    公开(公告)号:CA1049156A

    公开(公告)日:1979-02-20

    申请号:CA266526

    申请日:1976-11-24

    Applicant: IBM

    Abstract: IMPROVED METHOD FOR FORMING RECESSED REGIONS OF THERMALLY OXIDIZED SILICON AND STRUCTURES THEREOF An improved method for forming a recessed thermal SiO2 isolation region in a monocrystalline silicon semiconductor body having a major surface lying in a (100) plane as defined by the Miller indices by forming an etch resistant and oxidation resistant masking layer on the major surface of the body, forming at least one rectilinear annular opening in the masking layer, the opening being oriented with the sides parallel to the ¢100! directions on the major surface, removing a portion of the exposed body by anisotropic chemical etching, and oxidizing the resultant exposed portions of the body until the surface of the resultant SiO2 and major surface are substantially coplanar. A semiconductor device including a silicon substrate of a first conductivity, the major surface being in the (100) plane, an epitaxial silicon layer on the substrate, a lateral PN junction in the substrate, at least one annular rectangular shaped recessed SiO2 region in the epitaxial layer extending inwardly to the PN junction, the annular region being oriented with the sides parallel to the ¢100! directions on the major surface.

    METHOD OF FORMING INTEGRATED MOSFET DYNAMIC RANDOM ACCESS MEMORIES

    公开(公告)号:DE3174982D1

    公开(公告)日:1986-08-28

    申请号:DE3174982

    申请日:1981-10-09

    Applicant: IBM

    Abstract: A method of manufacturing LDD MOS FET RAM capable of delineating short (less than 1 micrometer) lightly doped drain regions. An N- implant is effected between gate electrodes and field oxide insulators, before the N+ implant. An insulator layer is then deposited also prior to N+ ion implantation. Reactive ion etching of the layer leaves narrow dimensioned insulator regions adjacent the gate electrode which serves to protect portions of the N- impurity region during the subsequent N+ implant. These protected regions are the lightly doped source/drain regions.

    6.
    发明专利
    未知

    公开(公告)号:FR2357067A1

    公开(公告)日:1978-01-27

    申请号:FR7716061

    申请日:1977-05-18

    Applicant: IBM

    Abstract: A method for forming monocrystalline silicon carbide on a silicon substrate by converting a portion of the monocrystalline silicon substrate into a porous silicon substance by anodic treatment carried out in an aqueous solution of hydrofluoric acid, heating the resultant substrate to a temperature in the range of 1050 DEG C to 1250 DEG C in an atmosphere that includes a hydrocarbon gas for a time sufficient to react the porous silicon and the gas, thereby forming a layer of monocrystalline silicon carbide on the silicon substrate.

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