公开(公告)号：DE3485457D1

公开(公告)日：1992-02-27

申请号：DE3485457

申请日：1984-11-14

Applicant: IBM

Inventor： ANANTHA NARASIPUR G ,  GAUR SANTOSH P ,  HUANG YI-SHIOU ,  TSANG PAUL J

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8224 ,  H01L29/08 ,  H01L29/735 ,  H01L21/00 ,  H01L21/82

Abstract: A method for making a lateral PNP transistor (simultaneously with an NPN transistor) and the resultant device wherein a first mask (76) defines a base-width by the resistor implant (78, 80) for a P-type resistor and a second mask (86) is overlaid asymmetricially on said first mask to partially cover the collector (80). At the same time that the NPN extrinsic base contact is made, P-type dopants-are introduced in the areas (88, 89) exposed by the first and second masks to provide an emitter (92) and a collector contact (94) for the PNP transistor, said transistor thus featuring a graded collector (96, 94) with a high punch-through voltage.

公开(公告)号：DE69018499D1

公开(公告)日：1995-05-18

申请号：DE69018499

申请日：1990-01-19

Applicant: IBM

Inventor： HABITZ PETER-ANTON ,  HSIEH CHANG-MING ,  HUANG YI-SHIOU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: A process of forming a lateral PNP transistor that includes the steps of: providing a chip of semicon-ductor material including an isolated N- device region (14) over a P substrate (16), with an N-epitaxial layer (20), a N+ buried subcollector (18), and a reach-through region (26); implanting N dopant material at a relatively low power and low dosage into a selected implant region (32), of the device region; implanting N dopant material at a relatively higher power and higher dosage into the implant region to form emitter and collector regions (34,36) in the device region such that an intrinsic base region (38), is defined there-between.

公开(公告)号：DE69018499T2

公开(公告)日：1995-11-09

申请号：DE69018499

申请日：1990-01-19

Applicant: IBM

Inventor： HABITZ PETER-ANTON ,  HSIEH CHANG-MING ,  HUANG YI-SHIOU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: A process of forming a lateral PNP transistor that includes the steps of: providing a chip of semicon-ductor material including an isolated N- device region (14) over a P substrate (16), with an N-epitaxial layer (20), a N+ buried subcollector (18), and a reach-through region (26); implanting N dopant material at a relatively low power and low dosage into a selected implant region (32), of the device region; implanting N dopant material at a relatively higher power and higher dosage into the implant region to form emitter and collector regions (34,36) in the device region such that an intrinsic base region (38), is defined there-between.