公开(公告)号：SG99845A1

公开(公告)日：2003-11-27

申请号：SG1998000852

申请日：1998-04-23

Applicant: IBM

Inventor： HORMAZDYAR MINOCHER DALAL ,  DU BINH NGUYEN ,  HAZARA SINGH RATHORE

IPC: H01L21/768 ,  H01L21/28 ,  H01L23/522

Abstract: The present invention relates to the field of semiconductor manufacturing, and more specifically to methods of forming sub-half-micron multi-level interconnect structures for integrated circuits. The inventive structure and process are spike free and that has resulted in improved circuit performance, reliability and process yields. The inventive structure and process have a plurality of insulator layers where each of the adjoining insulator layers are of a different material.

公开(公告)号：MY123847A

公开(公告)日：2006-06-30

申请号：MYPI19974824

申请日：1997-10-14

Applicant: IBM

Inventor： KENNETH MICHAEL FALLON ,  HORMAZDYAR MINOCHER DALAL ,  GENE JOSEPH GAUDENZI ,  CYNTHIA SUSAN MILKOVICH

IPC: H05K3/34 ,  H01L21/56 ,  H01L21/60 ,  H01L23/498 ,  H01L23/538 ,  H05K1/18 ,  H05K3/00 ,  H05K13/04

Abstract: A STRUCTURE AND METHOD IS DISCLOSED FOR DIRECTLY ATTACHING A DEVICE (42,44,46,48) OR PACKAGE ON FLEXIBLE ORGANIC CIRCUIT CARRIERS (23) HAVING LOW COST AND HIGH RELIABILITY.IC CHIPS WITH A NEW SOLDER INTERCONNECT STRUCTURE, COMPRISED OF A LAYER (43) OF PURE TIN, DEPOSITED ON THE TOP OF HIGH MELTING PB-SN SOLDER BALLS (41) ARE EMPLOYED FOR JOINING. THESE METHODS, TECHNIQUES AND METALLURGICAL STRUCTURES ENABLES DIRECT ATTACHMENT OF ELECTRONIC DEVICES OF ANY COMPLEXITY TO ANY SUBSTRATE AND TO ANY LEVEL OF PACKAGING HIERARCHY.ALSO, DEVICES OR PACKAGES HAVING OTHER JOINING TECHNOLOGIES, EG. SMT, BGA, TBGA, ETC. COULD BE JOINED ONTO THE FLEXIBLE CIRCUIT CARRIER.(FIG.6)

公开(公告)号：SG105511A1

公开(公告)日：2004-08-27

申请号：SG200105657

申请日：1993-02-01

Applicant: IBM

Inventor： RAJIV V JOSHI ,  JEROME J CUOMO ,  HORMAZDYAR MINOCHER DALAL ,  LOUIS L C HUS

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：SG115407A1

公开(公告)日：2005-10-28

申请号：SG200105658

申请日：1993-02-01

Applicant: IBM

Inventor： RAJIV V JOSHI ,  JEROME J CUOMO ,  HORMAZDYAR MINOCHER DALAL ,  LOUIS L C HSU

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L29/440 ,  H01L29/460

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：SG111047A1

公开(公告)日：2005-05-30

申请号：SG200201110

申请日：1993-02-01

Applicant: IBM

Inventor： RAJIV V JOSHI ,  JEROME J CUOMO ,  HORMAZDYAR MINOCHER DALAL ,  LOUIS L HSU

IPC: H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH 4 to WF 6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metallizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：MY116252A

公开(公告)日：2003-12-31

申请号：MYPI19981526

申请日：1998-04-06

Applicant: IBM

Inventor： HORMAZDYAR MINOCHER DALAL ,  DU BINH NGUYEN ,  HAZARA S RATHORE

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/441 ,  H01L23/522

Abstract: THE PRESENT INVENTION RELATES TO THE FIELD OF SEMICONDUCTOR MANUFACTURING, AND MORE SPECIFICALLY TO METHODS OF FORMING SUB-HALF-MICRON MULTI-LEVEL INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS. THE INVENTIVE STRUCTURE AND PROCESS ARE SPIKE FREE AND THAT HAS RESULTED IN IMPROVED CIRCUIT PERFORMANCE, RELIABILITY AND PROCESS YIELDS. THE INVENTIVE STRUCTURE AND PROCESS HAVE A PLURALITY OF INSULATOR LAYERS (39, 40, 49, 50, 59, 60) WHERE EACH OF THE ADJOINING INSULATOR LAYERS ARE OF A DIFFERENT MATERIAL. (FIGURE 8)