公开(公告)号：JP2008305403A

公开(公告)日：2008-12-18

申请号：JP2008147541

申请日：2008-06-05

Applicant: Internatl Business Mach Corp ,  Sony Computer Entertainment Inc ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  株式会社ソニー・コンピュータエンタテインメント

Inventor： FLACHS BRIAN ,  BRADLEY DOUGLAS HOOKER ,  DEMENT JONATHAN J ,  GERVAIS GILLES ,  DHONG SANG H ,  NISHINO YOICHI

IPC: G06F11/22 ,  G01R31/26 ,  G01R31/30 ,  G06F11/24

CPC classification number: G01R31/31721 ,  G01R31/31718

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for sorting processor chips based on a thermal design point. SOLUTION: Using this system and this method, for each processor chip, a high power workload is executed on the processor chip to determine a voltage regulator module (VRM) load curve. Thereafter, a thermal design point (TDP) workload is applied to the processor chip and the voltage is varied until performance of the processor chip falls on the VRM load curve. At this point, the power input to the processor chip is measured and used to carry out sorting/binning of the processor chip. The various workloads applied have a constant frequency. From this sorting of processor chips, high speed processors that require less voltage to achieve a desired frequency and low current processors that drain less current while running at a desired frequency can be identified. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种基于热设计点来分类处理器芯片的系统和方法。

解决方案：使用该系统和该方法，对于每个处理器芯片，在处理器芯片上执行高功率工作负载以确定电压调节器模块（VRM）负载曲线。 此后，将热设计点（TDP）工作负载应用于处理器芯片，并且电压变化，直到处理器芯片的性能落在VRM负载曲线上。 此时，对处理器芯片的功率输入进行测量并用于执行处理器芯片的分类/分样。 应用的各种工作负载具有恒定的频率。 从处理器芯片的这种排序中，可以识别需要较少电压以实现期望频率的低速处理器和在期望频率下运行时消耗较少电流的低电流处理器。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008004097A

公开(公告)日：2008-01-10

申请号：JP2007163089

申请日：2007-06-20

Applicant: Internatl Business Mach Corp ,  Sony Computer Entertainment Inc ,  Toshiba Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation ,  株式会社ソニー・コンピュータエンタテインメント ,  株式会社東芝

Inventor： MURAKI YOSUKE ,  TAMURA TETSUJI ,  TAKIGUCHI ITSUKI ,  AIKAWA MAKOTO ,  HAILU ESKINDER ,  KRAUTER BYRON LEE ,  WEITZEL STEPHEN DOUGLAS ,  QI JIEMING ,  MIKI KAZUHIKO ,  BOERSTLER DAVID WILLIAM ,  GERVAIS GILLES ,  PETERSON KIRK DAVID ,  BERRY ROBERT WALTER JR ,  DHONG SANG HOO

IPC: G06F1/06 ,  G06F1/26 ,  G06F1/32 ,  G06F15/78

CPC classification number: G06F1/04

Abstract: PROBLEM TO BE SOLVED: To reduce power supply voltage to be supplied to a microprocessor. SOLUTION: The present invention relates to a technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed (S120-S140). In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is operable. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：减少供应给微处理器的电源电压。 解决方案：本发明涉及一种向微处理器提供电源电压的技术。 在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理（S120-S140）。 在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器可操作的电源电压最小化。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：DE4244275C1

公开(公告)日：1994-07-21

申请号：DE4244275

申请日：1992-12-28

Applicant: IBM

Inventor： GERVAIS GILLES ,  HOLM INGEMAR DIPL ING ,  KOHLER HELMUT DIPL ING ,  KOEHLER THOMAS DIPL ING ,  SCHUMACHER NORBERT DIPL ING ,  ZILLES GERHARD DIPL ING

IPC: G06F7/00 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G11C29/10 ,  G11C29/24 ,  G11C29/00 ,  G06F11/08

Abstract: PCT No. PCT/EP93/03572 Sec. 371 Date Aug. 10, 1995 Sec. 102(e) Date Aug. 10, 1995 PCT Filed Dec. 15, 1993 PCT Pub. No. WO94/15290 PCT Pub. Date Jul. 7, 1994Discloses a device and a method for checking by means of a checker (100). the data incorporating check bits read into a memory stack. The device comprises a first counter (20), which is connected through logical gates (30a-d) with some of the memory input lines (25), and a second counter (80) between the checker (100) and the memory (50), which is connected through logical gates (70a-d) to the memory output lines (55) corresponding to the memory input lines (25) with the first (20) and the second (80). counters generating continuous binary values. The method comprising the following stages: combination of the data to be read in with a value generated by a first counter (20) in accordance with an exclusive-OR operation; reading the logically combined data into the memory (50); reading the logically combined data from the memory (50); combination of the logically combined data read out with a value generated by a second counter (80) in accordance with an exclusive-OR operation; checking the data read out for parity in a parity checker (100). The invention may be used in a buffer memory (50) between two asynchronously timed buses.