公开(公告)号：DE69831282T2

公开(公告)日：2006-08-10

申请号：DE69831282

申请日：1998-02-05

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS JOERG DIPL ING ,  KOEHLER THOMAS DIPL ING ,  PFEFFER ERWIN DIPL ING

IPC: G06F9/38 ,  G06F9/30

Abstract: The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain logical register, said logical register will have to be represented by a multitude of physical registers. Therefore, there have to exist several physical rename registers per logical register. The oldest one of said rename registers defines the architected state of the computer system, the in-order state. The invention provides a method for administration of the various register instances. Both the registers representing the in-order state and the various rename instances are kept in one common circular buffer. There exist two pointers per logical register: The first one, the in-order pointer, points to the register that represents the in-order state, the second one, the rename pointer, points to the most recent rename instance.

公开(公告)号：DE4244275C1

公开(公告)日：1994-07-21

申请号：DE4244275

申请日：1992-12-28

Applicant: IBM

Inventor： GERVAIS GILLES ,  HOLM INGEMAR DIPL ING ,  KOHLER HELMUT DIPL ING ,  KOEHLER THOMAS DIPL ING ,  SCHUMACHER NORBERT DIPL ING ,  ZILLES GERHARD DIPL ING

IPC: G06F7/00 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G11C29/10 ,  G11C29/24 ,  G11C29/00 ,  G06F11/08

Abstract: PCT No. PCT/EP93/03572 Sec. 371 Date Aug. 10, 1995 Sec. 102(e) Date Aug. 10, 1995 PCT Filed Dec. 15, 1993 PCT Pub. No. WO94/15290 PCT Pub. Date Jul. 7, 1994Discloses a device and a method for checking by means of a checker (100). the data incorporating check bits read into a memory stack. The device comprises a first counter (20), which is connected through logical gates (30a-d) with some of the memory input lines (25), and a second counter (80) between the checker (100) and the memory (50), which is connected through logical gates (70a-d) to the memory output lines (55) corresponding to the memory input lines (25) with the first (20) and the second (80). counters generating continuous binary values. The method comprising the following stages: combination of the data to be read in with a value generated by a first counter (20) in accordance with an exclusive-OR operation; reading the logically combined data into the memory (50); reading the logically combined data from the memory (50); combination of the logically combined data read out with a value generated by a second counter (80) in accordance with an exclusive-OR operation; checking the data read out for parity in a parity checker (100). The invention may be used in a buffer memory (50) between two asynchronously timed buses.