公开(公告)号：DE69019822D1

公开(公告)日：1995-07-06

申请号：DE69019822

申请日：1990-06-27

Applicant: IBM

Inventor： SCHUMACHER NORBERT W DIPL ING ,  HOLM INGEMAR DIPL ING ,  ZILLES GERHARD D- JETTINGEN DI ,  MANNHERZ PETER DIPL ING ,  KOHLER HELMUT DIPL ING

IPC: G06F12/16 ,  G06F11/10 ,  G11C8/04

Abstract: A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.

公开(公告)号：DE4244275C1

公开(公告)日：1994-07-21

申请号：DE4244275

申请日：1992-12-28

Applicant: IBM

Inventor： GERVAIS GILLES ,  HOLM INGEMAR DIPL ING ,  KOHLER HELMUT DIPL ING ,  KOEHLER THOMAS DIPL ING ,  SCHUMACHER NORBERT DIPL ING ,  ZILLES GERHARD DIPL ING

IPC: G06F7/00 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G11C29/10 ,  G11C29/24 ,  G11C29/00 ,  G06F11/08

Abstract: PCT No. PCT/EP93/03572 Sec. 371 Date Aug. 10, 1995 Sec. 102(e) Date Aug. 10, 1995 PCT Filed Dec. 15, 1993 PCT Pub. No. WO94/15290 PCT Pub. Date Jul. 7, 1994Discloses a device and a method for checking by means of a checker (100). the data incorporating check bits read into a memory stack. The device comprises a first counter (20), which is connected through logical gates (30a-d) with some of the memory input lines (25), and a second counter (80) between the checker (100) and the memory (50), which is connected through logical gates (70a-d) to the memory output lines (55) corresponding to the memory input lines (25) with the first (20) and the second (80). counters generating continuous binary values. The method comprising the following stages: combination of the data to be read in with a value generated by a first counter (20) in accordance with an exclusive-OR operation; reading the logically combined data into the memory (50); reading the logically combined data from the memory (50); combination of the logically combined data read out with a value generated by a second counter (80) in accordance with an exclusive-OR operation; checking the data read out for parity in a parity checker (100). The invention may be used in a buffer memory (50) between two asynchronously timed buses.

公开(公告)号：DE69019822T2

公开(公告)日：1995-12-14

申请号：DE69019822

申请日：1990-06-27

Applicant: IBM

Inventor： SCHUMACHER NORBERT W DIPL ING ,  HOLM INGEMAR DIPL ING ,  ZILLES GERHARD D- JETTINGEN DI ,  MANNHERZ PETER DIPL ING ,  KOHLER HELMUT DIPL ING

IPC: G06F12/16 ,  G06F11/10 ,  G11C8/04

Abstract: A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.