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公开(公告)号：DE69019822D1
公开(公告)日：1995-07-06
申请号：DE69019822
申请日：1990-06-27
Applicant: IBM
Inventor： SCHUMACHER NORBERT W DIPL ING , HOLM INGEMAR DIPL ING , ZILLES GERHARD D- JETTINGEN DI , MANNHERZ PETER DIPL ING , KOHLER HELMUT DIPL ING
Abstract: A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.
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公开(公告)号：DE4244275C1
公开(公告)日：1994-07-21
申请号：DE4244275
申请日：1992-12-28
Applicant: IBM
Inventor： GERVAIS GILLES , HOLM INGEMAR DIPL ING , KOHLER HELMUT DIPL ING , KOEHLER THOMAS DIPL ING , SCHUMACHER NORBERT DIPL ING , ZILLES GERHARD DIPL ING
Abstract: PCT No. PCT/EP93/03572 Sec. 371 Date Aug. 10, 1995 Sec. 102(e) Date Aug. 10, 1995 PCT Filed Dec. 15, 1993 PCT Pub. No. WO94/15290 PCT Pub. Date Jul. 7, 1994Discloses a device and a method for checking by means of a checker (100). the data incorporating check bits read into a memory stack. The device comprises a first counter (20), which is connected through logical gates (30a-d) with some of the memory input lines (25), and a second counter (80) between the checker (100) and the memory (50), which is connected through logical gates (70a-d) to the memory output lines (55) corresponding to the memory input lines (25) with the first (20) and the second (80). counters generating continuous binary values. The method comprising the following stages: combination of the data to be read in with a value generated by a first counter (20) in accordance with an exclusive-OR operation; reading the logically combined data into the memory (50); reading the logically combined data from the memory (50); combination of the logically combined data read out with a value generated by a second counter (80) in accordance with an exclusive-OR operation; checking the data read out for parity in a parity checker (100). The invention may be used in a buffer memory (50) between two asynchronously timed buses.
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Patent Agency Ranking
公开(公告)号：DE69019822T2
公开(公告)日：1995-12-14
申请号：DE69019822
申请日：1990-06-27
Applicant: IBM
Inventor： SCHUMACHER NORBERT W DIPL ING , HOLM INGEMAR DIPL ING , ZILLES GERHARD D- JETTINGEN DI , MANNHERZ PETER DIPL ING , KOHLER HELMUT DIPL ING
Abstract: A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.
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公开(公告)号：DE69029390D1
公开(公告)日：1997-01-23
申请号：DE69029390
申请日：1990-09-15
Applicant: IBM
Inventor： KOHLER HELMUT DIPL ING , SCHUMACHER NORBERT DIPL ING
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公开(公告)号：DE68905475D1
公开(公告)日：1993-04-22
申请号：DE68905475
申请日：1989-07-18
Applicant: IBM
Inventor： KLINK ERICH DIPL ING , KOHLER HELMUT DIPL ING , PROSS HARALD DIPL ING
IPC: H01L23/50 , H01L23/495 , H01L23/498 , H01L25/065
Abstract: A method and a memory module are provided which allow the duplication of the density of a memory module with a minimum of increasing of the module size and with low manufacturing costs. The method uses well-known techniques which are used by the manufacturing of DIP modules containing only one chip inside the moulded plastic or ceramic housing. Contrary to with the common methods the inner bond leads are punched so that they have a greater width than the common inner bond leads. Subsequently or together with the punching step the inner bond leads are slotted in order to allow the bending of at least one of each of the smaller inner bond leads obtained before for providing a space between the two inner bond leads. Next, two semiconductor memory chips are glued together back-to-back and inserted in the gap between the upper inner bond leads and the lower inner bond leads so that the upper and lower bond leads embrace the two chips. The chips can be equal with the pad occupation, or mirrored. The method is applicable to dual inline package (DIP) as well as to ZIG-ZAG package. The semiconductor memory module comprises a housing (4) of plastic or ceramic in which two chips (8, 10) are stacked together back-to-back. The pads (20) of the chips are electrically connected by wire-bonding to beam leads (14) which comprise outer bond leads (6), generally arranged outside the housing to form the ocntact pins or contact leads of the module to a printed circuit board, and inner bond leads (16) in the housing. The inner bond leads are spread in the area of the inner lead bond ends into upper (16a) and lower (16b) bond leads forming a gap (22) for receiving and embracing the stacked chips.
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公开(公告)号：DE69029390T2
公开(公告)日：1997-06-12
申请号：DE69029390
申请日：1990-09-15
Applicant: IBM
Inventor： KOHLER HELMUT DIPL ING , SCHUMACHER NORBERT DIPL ING
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公开(公告)号：DE68905475T2
公开(公告)日：1993-09-16
申请号：DE68905475
申请日：1989-07-18
Applicant: IBM
Inventor： KLINK ERICH DIPL ING , KOHLER HELMUT DIPL ING , PROSS HARALD DIPL ING
IPC: H01L23/50 , H01L23/495 , H01L23/498 , H01L25/065
Abstract: A method and a memory module are provided which allow the duplication of the density of a memory module with a minimum of increasing of the module size and with low manufacturing costs. The method uses well-known techniques which are used by the manufacturing of DIP modules containing only one chip inside the moulded plastic or ceramic housing. Contrary to with the common methods the inner bond leads are punched so that they have a greater width than the common inner bond leads. Subsequently or together with the punching step the inner bond leads are slotted in order to allow the bending of at least one of each of the smaller inner bond leads obtained before for providing a space between the two inner bond leads. Next, two semiconductor memory chips are glued together back-to-back and inserted in the gap between the upper inner bond leads and the lower inner bond leads so that the upper and lower bond leads embrace the two chips. The chips can be equal with the pad occupation, or mirrored. The method is applicable to dual inline package (DIP) as well as to ZIG-ZAG package. The semiconductor memory module comprises a housing (4) of plastic or ceramic in which two chips (8, 10) are stacked together back-to-back. The pads (20) of the chips are electrically connected by wire-bonding to beam leads (14) which comprise outer bond leads (6), generally arranged outside the housing to form the ocntact pins or contact leads of the module to a printed circuit board, and inner bond leads (16) in the housing. The inner bond leads are spread in the area of the inner lead bond ends into upper (16a) and lower (16b) bond leads forming a gap (22) for receiving and embracing the stacked chips.
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