公开(公告)号：EP1671339A4

公开(公告)日：2007-11-21

申请号：EP04794665

申请日：2004-10-08

Applicant: IBM

Inventor： CHEN BING ,  GOULD SCOTT W ,  HSU MARK KWANG-JEN ,  RYAN PATRICK M ,  SCHANZENBACH ERICH C

IPC: G06F17/50 ,  H01L23/528

CPC classification number: G06F17/5077 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid (31) is generated for a voltage island on metal levels 1 to N-1. Then a second power grid is generated on metal levels N and above (32). A bounding region of the second robust power grid is determined (33). Finally, the shortest distance connections from a set of power sources is routed to the second power grid (34).

公开(公告)号：EP1649493A4

公开(公告)日：2010-04-14

申请号：EP04777801

申请日：2004-07-08

Applicant: IBM

Inventor： BEDNAR THOMAS R ,  GOULD SCOTT W ,  LACKEY DAVID E ,  STOUT DOUGLAS W ,  ZUCHOWSKI PAUL S

IPC: G06F17/50 ,  G06F1/26 ,  G06F9/45 ,  G11C5/14 ,  H01L20060101 ,  H01L23/528 ,  H01L27/02 ,  H02J3/38

CPC classification number: H01L23/5286 ,  G11C5/14 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2003188260A

公开(公告)日：2003-07-04

申请号：JP2002283744

申请日：2002-09-27

Applicant: IBM

Inventor： GOULD SCOTT W ,  HONSINGER PHILIP S ,  HUBER ANDREW D ,  RYAN PATRICK M

IPC: G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To provide a method for routing power supply from a power supply network to one or more power supply terminal in a voltage land. SOLUTION: The method for routing power supply comprises a step for dividing a power supply network into segments, a step for forming power supply terminal/segment connecting parts based on a first set of criteria, a step for eliminating selected power supply terminal/segment connecting parts based on a second set of criteria, and a step for selecting one power supply terminal/ segment connecting part for each power supply terminal wherein a first criterion includes limitation of power drop, limitation of wiring length, limitation of wiring size, and limitation of wiring layer whereas a second criterion includes electromigration, wiring length and current criterion. COPYRIGHT: (C)2003,JPO

公开(公告)号：WO2005008725A3

公开(公告)日：2006-11-23

申请号：PCT/US2004021943

申请日：2004-07-08

Applicant: IBM ,  BEDNAR THOMAS R ,  GOULD SCOTT W ,  LACKEY DAVID E ,  STOUT DOUGLAS W ,  ZUCHOWSKI PAUL S

Inventor： BEDNAR THOMAS R ,  GOULD SCOTT W ,  LACKEY DAVID E ,  STOUT DOUGLAS W ,  ZUCHOWSKI PAUL S

IPC: G06F17/50 ,  G06F9/45 ,  H01L20060101 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L23/5286 ,  G11C5/14 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit comprising: a parent terrain (element 12); and a hierarchal order of nested voltage islands within the parent terrain (element 12), each higher-order voltage island nested (Figure 5, element 32) within a lower-order voltage island (Figure 5), each nested voltage island (Figure 5, element 32) having the same hierarchal structure.

Abstract translation: 一种集成电路，包括：母地形（元件12）; 以及在主地形（元件12）内的嵌套电压岛的层级顺序，在低阶电压岛（图5）内的每个高阶电压岛嵌套（图5，元件32），每个嵌套电压岛（图5 ，元件32）具有相同的层级结构。

公开(公告)号：WO2005036606A2

公开(公告)日：2005-04-21

申请号：PCT/US2004033384

申请日：2004-10-08

Applicant: IBM ,  CHEN BING ,  GOULD SCOTT W ,  HSU MARK KWANG-JEN ,  RYAN PATRICK M ,  SCHANZENBACH ERICH C

Inventor： CHEN BING ,  GOULD SCOTT W ,  HSU MARK KWANG-JEN ,  RYAN PATRICK M ,  SCHANZENBACH ERICH C

IPC: G06F17/50 ,  H01L23/528 ,  H01L

CPC classification number: G06F17/5077 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid (31) is generated for a voltage island on metal levels 1 to N-1. Then a second power grid is generated on metal levels N and above (32). A bounding region of the second robust power grid is determined (33). Finally, the shortest distance connections from a set of power sources is routed to the second power grid (34).

Abstract translation: 公开了一种在集成电路芯片内的电压岛上执行电力布线的方法。 为金属1至N-1上的电压岛产生第一电网（31）。 然后在金属水平N及以上（32）上产生第二个电网。 确定第二鲁棒电网的边界区域（33）。 最后，将一组电源的最短距离连接路由到第二电网（34）。