公开(公告)号：FR2349887A1

公开(公告)日：1977-11-25

申请号：FR7706853

申请日：1977-03-02

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  HOOD MICHAEL I DAVIS ET ROBERT ,  GRAYBIEL LYNN A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

IPC: G06F12/14 ,  G06F12/02 ,  G06F13/00

公开(公告)号：CA1081859A

公开(公告)日：1980-07-15

申请号：CA275573

申请日：1977-04-05

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  HOOD ROBERT A ,  GRAYBIEL LYNN A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

IPC: G06F12/14 ,  G06F12/02 ,  G06F9/20

Abstract: KEY CONTROLLED ADDRESS RELOCATION TRANSLATION SYSTEM Translates each active address key (AAK) into a respective addressability in physical main memory. Each addressability comprises one or more physical blocks which may be scattered in the main memory. Address keys are contained in plural key register sections, and AAK select circuits outgate to the translator each M K from a key register section corresponding to the access type for each storage access request currently received from a processor or I/O channel. Each address key identifies a particular stack of one or more segmentation registers. Each segmentation register can be assigned the address of any segment (i.e. a block of contiguous physical addresses located anywhere in the main memory). Each segmentation register also has validity and read-only flag bits for its assigned block. Each stack can translate a contiguous set of logical program addresses into physical addresses. Any stack can support all logical addresses apparent to a program, although the machine can cause a single program to access plural addressabilities due to the machine assignment of address keys. For each storage access request for a logical program address, a stack is addressed by the AAK to determine an addressability. Then a register in the stack is addressed by high-order bits in the logical program address. The addressed register outputs the translated block address. The main memory can have any physical size in relation to the number of stacks, and to the number of segmentation registers in each stack.

公开(公告)号：FR2357981A1

公开(公告)日：1978-02-03

申请号：FR7706852

申请日：1977-03-02

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  GRAYBIEL LYNN A ,  HOOD ROBERT A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

IPC: G06F9/312 ,  G06F11/00 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24 ,  G11C8/00 ,  G06F9/20

Abstract: The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

公开(公告)号：FR2349882A1

公开(公告)日：1977-11-25

申请号：FR7707430

申请日：1977-03-04

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  OSBORNE WILLIAM S ,  GRAYBIEL LYNN A

IPC: G06F11/00 ,  G06F9/46 ,  G06F9/48 ,  G06F9/18

公开(公告)号：CA1078068A

公开(公告)日：1980-05-20

申请号：CA275571

申请日：1977-04-05

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  GRAYBIEL LYNN A ,  HOOD ROBERT A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

IPC: G06F9/312 ,  G06F11/00 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24 ,  G06F9/00

Abstract: ADDRESS KEY REGISTER LOAD/STORE INSTRUCTION SYSTEM Instruction operated controls for loading or storing key values into or from one or more key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register(GPR). Both the load or store controls can be operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

公开(公告)号：CA1075366A

公开(公告)日：1980-04-08

申请号：CA275542

申请日：1977-04-05

Applicant: IBM

Inventor： BIRNEY RICHARD E ,  OSBORNE WILLIAM S ,  GRAYBIEL LYNN A

IPC: G06F11/00 ,  G06F9/46 ,  G06F9/48 ,  G06F9/20

Abstract: A control circuit arrangement for storing the addressability currently being accessed by a processor by inputting and storing each processor active address key (AAK) in a last AAK register. When a hard or soft check interrupt occurs, the interrupted addressability is saved as the processor's last key saved (i.e LKSA) in the processor last AAK register. A hard or soft check interrupt includes a machine check interrupt, a program check interrupt, or a software exception. The interrupted addressability in then connected to the supervisor addressability by gating the LKSA into the source operand key section in the AKR from the processor's last AAK register, and setting the supervisor key into the other sections of the AKR, in preparation for performing certain supervisor operations. Until the LKSA gating into the AKR is completed, no AAK is ingated into the last AAK register. Thereafter the ingating by the last AAK register is resumed when the processor generates either a machine check reset, program check reset, or system reset.