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    4.
    发明专利
    未知

    公开(公告)号：FR2357981A1

    公开(公告)日：1978-02-03

    申请号：FR7706852

    申请日：1977-03-02

    Applicant: IBM

    Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  GRAYBIEL LYNN A ,  HOOD ROBERT A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

    IPC: G06F9/312 ,  G06F11/00 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24 ,  G11C8/00 ,  G06F9/20

    Abstract: The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

    KEY CONTROLLED ADDRESS RELOCATION TRANSLATION SYSTEM
    5.
    发明专利
    KEY CONTROLLED ADDRESS RELOCATION TRANSLATION SYSTEM 未知

    公开(公告)号：CA1081859A

    公开(公告)日：1980-07-15

    申请号：CA275573

    申请日：1977-04-05

    Applicant: IBM

    Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  HOOD ROBERT A ,  GRAYBIEL LYNN A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

    IPC: G06F12/14 ,  G06F12/02 ,  G06F9/20

    Abstract: KEY CONTROLLED ADDRESS RELOCATION TRANSLATION SYSTEM Translates each active address key (AAK) into a respective addressability in physical main memory. Each addressability comprises one or more physical blocks which may be scattered in the main memory. Address keys are contained in plural key register sections, and AAK select circuits outgate to the translator each M K from a key register section corresponding to the access type for each storage access request currently received from a processor or I/O channel. Each address key identifies a particular stack of one or more segmentation registers. Each segmentation register can be assigned the address of any segment (i.e. a block of contiguous physical addresses located anywhere in the main memory). Each segmentation register also has validity and read-only flag bits for its assigned block. Each stack can translate a contiguous set of logical program addresses into physical addresses. Any stack can support all logical addresses apparent to a program, although the machine can cause a single program to access plural addressabilities due to the machine assignment of address keys. For each storage access request for a logical program address, a stack is addressed by the AAK to determine an addressability. Then a register in the stack is addressed by high-order bits in the logical program address. The addressed register outputs the translated block address. The main memory can have any physical size in relation to the number of stacks, and to the number of segmentation registers in each stack.

    Data processing system with address translator arrangement
    6.
    发明专利
    Data processing system with address translator arrangement 未知

    公开(公告)号：CH617523A5

    公开(公告)日：1980-05-30

    申请号：CH532977

    申请日：1977-04-28

    Applicant: IBM

    Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN ,  GRAYBIEL LYNN ALLAN ,  KAHN SAMUEL ,  OSBORNE WILLIAM STEESE ,  HOOD ROBERT ALLEN ,  BOURKE DONALL GERRAID

    IPC: G06F12/02 ,  G06F9/36

    Abstract: In a data processing system with translation of the logic addresses, predetermined in the programs, into the physical addresses necessary for memory access, special devices are provided by means of which flexible allocation of address areas for various categories of information or various types of programs is possible. The address translator arrangement has a separate translator unit (stack 0... stack 7) for each address area. In addition, an arrangement (20...35) for storing various address keys for various categories of information and for outputting one of these keys each on the basis of present memory access control signals is provided. One of the translator units is then in each case selected with the aid of the output address key by means of an additional selection device (40). This makes it possible to obtain different physical addresses from the same logic address during the translation, dependently on which category of information is to be accessed at the time and dependently on the address key in each case allocated to the category of information.

    ADDRESS KEY REGISTER LOAD/STORE INSTRUCTION SYSTEM
    7.
    发明专利
    ADDRESS KEY REGISTER LOAD/STORE INSTRUCTION SYSTEM 未知

    公开(公告)号：CA1078068A

    公开(公告)日：1980-05-20

    申请号：CA275571

    申请日：1977-04-05

    Applicant: IBM

    Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  GRAYBIEL LYNN A ,  HOOD ROBERT A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

    IPC: G06F9/312 ,  G06F11/00 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24 ,  G06F9/00

    Abstract: ADDRESS KEY REGISTER LOAD/STORE INSTRUCTION SYSTEM Instruction operated controls for loading or storing key values into or from one or more key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register(GPR). Both the load or store controls can be operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

    Data processing system in which keys are used for memory access
    8.
    发明专利
    Data processing system in which keys are used for memory access 未知

    公开(公告)号：CH613789A5

    公开(公告)日：1979-10-15

    申请号：CH533077

    申请日：1977-04-28

    Applicant: IBM

    Inventor： BIRNEY RICHARD EUGENE ,  DABIS MICHAEL IAN ,  GRAYBIEL LYNN ALLAN ,  HOOD ROBERT ALLEN ,  KAHN SAMUEL ,  OSBORNE WILLIAM STEESE ,  MCDERMOTT THOMAS STEPHEN ,  WISE LARRY EDWARD

    IPC: G06F9/312 ,  G06F12/14 ,  G06F13/12 ,  G06F9/06

    Abstract: In the data processing system, one section each (32, 33, 34, 35) of a key register is provided for different types of memory access. A selection circuit (20), the data inputs of which are connected to the key register sections and the control inputs of which are connected to memory access selection signal lines (22, 23, 24, 25) of one or more processors, can be used to select an active memory access key in each case, depending on the type of access. An additional section (31) of the key register is provided for cycle-stealing accesses (memory accesses by a peripheral device without formal program interrupt) and connected to a data input of the selection circuit (20) so that an active memory access key can be selected by means of access signals on a selection signal line (21), connected to another control input of the selection circuit, of an input/output channel mechanism, also including I/O cycle stealing accesses.

    ADDRESS KEY REGISTER LOAD/STORE INSTRUCTION SYSTEMS
    9.
    发明专利
    ADDRESS KEY REGISTER LOAD/STORE INSTRUCTION SYSTEMS 未知

    公开(公告)号：AU2474777A

    公开(公告)日：1978-11-09

    申请号：AU2474777

    申请日：1977-05-02

    Applicant: IBM

    Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN ,  GRAYBIEL LYNN ALLAN ,  HOOD ROBERT ALLEN ,  OSBORNE WILLIAM STEESE ,  KAHN SAMUEL

    IPC: G06F9/312 ,  G06F11/00 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24 ,  G06F13/06

    Abstract: The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

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