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    INCREASING ELECTROMIGRATION LIFETIME AND CURRENT DENSITY IN IC
    1.
    发明申请
    INCREASING ELECTROMIGRATION LIFETIME AND CURRENT DENSITY IN IC 审中-公开
    增加集成电路的电迁移寿命和电流密度

    公开(公告)号：WO2007045568A3

    公开(公告)日：2007-07-12

    申请号：PCT/EP2006067144

    申请日：2006-10-06

    Applicant: IBM ,  IBM UK ,  GRECO STEPHEN ,  HU CHAO-KUN ,  MCLAUGHLIN PAUL

    Inventor： GRECO STEPHEN ,  HU CHAO-KUN ,  MCLAUGHLIN PAUL

    IPC: H01L23/522

    CPC classification number: H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.

    Abstract translation: 公开了具有增加的电迁移寿命和容许电流密度的集成电路及其形成方法。 在一个实施例中，集成电路包括连接到至少一个功能通孔的导线和至少一个伪通孔，所述至少一个伪通孔具有电连接到导线的第一下端和与任何导电不电连接（隔离）的第二上端 线。 每个虚拟通孔从导线垂直向上延伸，并去除快速扩散路径的一部分，即金属对电介质盖界面，其由金属对金属衬里界面取代。 结果，每个虚拟通孔降低了金属扩散速率并因此增加了电迁移寿命并允许增加电流密度。

    6.
    发明专利
    未知

    公开(公告)号：AT504084T

    公开(公告)日：2011-04-15

    申请号：AT06778036

    申请日：2006-07-27

    Applicant: IBM

    Inventor： BREARLEY WILLIAM ,  GRECO STEPHEN ,  SANKARAN SUJATHA ,  STANDAERT THEODORUS

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A method and structure for a composite stud contact interface with a decreased contact resistance and improved reliability. A selective dry etch is used which comprises a fluorine containing gas. The contact resistance is reduced by partially dry-etching back the tungsten contact after or during the M1 RIE process. The recessed contact is then subsequently metalized during the M1 liner/plating process. The tungsten contact height is reduced after it has been fully formed.

    7.
    发明专利
    未知

    公开(公告)号：AT463046T

    公开(公告)日：2010-04-15

    申请号：AT06760152

    申请日：2006-05-19

    Applicant: IBM

    Inventor： GRECO STEPHEN ,  STANDAERT THEODORUS

    IPC: H01L21/768 ,  H01L23/528

    Abstract: Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed. In one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit using a dual damascene structure in a first dielectric layer, and BEOL wiring over a second circuit using a single damascene via structure in the first dielectric layer. Then, simultaneously generating BEOL wiring over the first circuit using a dual damascene structure in a second dielectric layer, and BEOL wiring over the second circuit using a single damascene line wire structure in the second dielectric layer. The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures. A semiconductor product having different width BEOL wiring for different circuits is also disclosed.

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