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    Glass-annealing process for encapsulating and stabilizing fet devices
    8.
    发明授权
    Glass-annealing process for encapsulating and stabilizing fet devices 失效
    用于封装和稳定FET器件的玻璃退火工艺

    公开(公告)号：US3658678A

    公开(公告)日：1972-04-25

    申请号：US3658678D

    申请日：1969-11-26

    Applicant: IBM

    Inventor： GREGOR LAWRENCE V ,  ZUEGEL MARKUS

    IPC: H01L29/78 ,  C23C14/10 ,  H01J37/34 ,  H01L21/316 ,  H01L23/29 ,  H01L29/00 ,  C23C15/00

    CPC classification number: H01L23/291 ,  C23C14/10 ,  H01J37/3402 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/31612 ,  H01L29/00 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A process is described for passivating completed FET devices by encapsulation. High purity silicon dioxide is deposited on the completed field effect transistor (FET) device by the RF sputtering of a high purity silicon dioxide target in an inert atmosphere. The sputtered silicon dioxide layer is made approximately 1.5 times the thickness of the FET gate. Then, the device is annealed in a non-oxidizing atmosphere to restore the threshold voltage of the FET to its desired value prior to sputtering. Appropriate ranges are disclosed for the values of the temperature and the RF power density of the sputtering step and for the temperature and the time of the annealing step.

    Abstract translation: 描述了通过封装钝化完成的FET器件的过程。 通过在惰性气氛中的高纯度二氧化硅靶的RF溅射，在完整的场效应晶体管（FET）器件上沉积高纯二氧化硅。 溅射的二氧化硅层约为FET栅极厚度的1.5倍。 然后，在非氧化气氛下对器件进行退火，在溅射之前将FET的阈值电压恢复到其期望值。 对于溅射步骤的温度和RF功率密度的值以及退火步骤的温度和时间，公开了适当的范围。

    INTEGRATED CIRCUIT ARRANGEMENT USING PREFORMED SEMICONDUCTOR WAFER
    9.
    发明专利
    INTEGRATED CIRCUIT ARRANGEMENT USING PREFORMED SEMICONDUCTOR WAFER 未知

    公开(公告)号：CA948329A

    公开(公告)日：1974-05-28

    申请号：CA948381

    申请日：1965-12-22

    Applicant: IBM

    Inventor： CAMPAGNA FRANK J ,  GREGOR LAWRENCE V ,  SERAPHIM DONALD P

    IPC: H01L21/316 ,  H01L49/02 ,  H01L1/14

    Abstract: 1,095,413. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 8, 1965 [Dec. 24, 1964], No. 47223/65. Heading H1K. Parts of a layer of semi-conductor material forming components of an integrated circuit are isolated by etching deep grooves between them and filling the grooves with insulating material. An N-type silicon substrate 1a has a P-type epitaxial layer 1b deposited on one surface by thermal decomposition of silicon tetrachloride using hydrogen as a carrier gas. The surface of layer 1b is covered with a photo-resist which is exposed and developed, Fig. 2A (not shown). The wafer is then etched using a mixture of nitric, hydrofluoric and acetic acids to expose the substrate, Fig. 2B (not shown). The surface is masked using a thermally grown oxide layer and phosphorus is diffused-in to form highly conductive connection regions (5) extending across the floors of etched grooves (B) and up the sides of the islands (R), Fig. 2D (not shown). The oxide mask is removed and the device anodized, using sulphuric acid and a platinum cathode, to form a thick layer (7) of silicon dioxide which at least fills grooves (B), Fig. 2E (not shown). The surface of oxide layer (7) is masked with a photo-resist (25) Fig. 2F (not shown), and is etched to expose the surfaces of the islands (R), Fig. 2G (not shown), to provide a reference level. The surface of the wafer is lapped to this reference level and chemically polished using sodium hydroxide, Fig. 2E (not shown). An oxide layer 9 is then formed on the surface of the wafer and transistors are formed by diffusion in selected islands A, Fig. 1C. Interconnections are formed by vapour depositing strips 13 of aluminium or molybdenum over the oxide layer, crossovers being effected by contacting the ends of diffused connection regions 5 and depositing the crossing connections on top of oxide layer 7 at right angles to region 5. The arrangement of an AND-INVERT gate is illustrated, Figs. 1A and 1D (not shown), in which four transistors (T1 to T4) are formed in islands (A), while the diffused connection regions (5) extend between smaller islands (C) on which connections are made between deposited conductors and regions (5). Thin film resistors (3, 3 1 ) are deposited on top of oxide layer (7) and extend at right angles to the direction of regions (5).

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