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    COMPRESSIVE SIGE <110> GROWTH AND STRUCTURE OF MOSFET DEVICES
    1.
    发明公开
    COMPRESSIVE SIGE <110> GROWTH AND STRUCTURE OF MOSFET DEVICES 审中-公开
    KOMPRESSIVES SIGE- <110> -WACHSTUM UND STRUKTURFÜRMOSFET-BAUELEMENTE

    公开(公告)号：EP1794786A4

    公开(公告)日：2008-12-24

    申请号：EP05785191

    申请日：2005-06-21

    Applicant: IBM

    Inventor： CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

    IPC: H01L29/04 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/036 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L29/045 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/823807 ,  H01L29/1054

    Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psuedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600ºC and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described comprising the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HC1 acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a RMS roughness of less than 0.1 nm.

    Abstract translation: 描述了一种用于导电载体的结构和形成方法，该结构包括在<110>中具有上表面的Si或SiGe的单晶衬底以及具有不同于衬底的Ge浓度的伪晶体或外延层，由此该伪晶体层 正处于紧张状态。 描述了用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中形成假性或外延层的步骤，通过将工具中的温度提高至约600℃并且将含Si气体和Ge 含有气体。 描述了用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底分别浸入一系列含有臭氧，稀HF，去离子水，HCl酸和去离子水的浴中，接着在惰性气氛中干燥衬底 以获得无杂质且具有小于0.1nm的RMS粗糙度的基材表面。

    Self-aligned soi with different crystal orientation using wafer bonding and simox process
    3.
    发明专利
    Self-aligned soi with different crystal orientation using wafer bonding and simox process 有权
    使用波形粘结和SIMOX工艺的具有不同晶体取向的自对准SOI

    公开(公告)号：JP2005057284A

    公开(公告)日：2005-03-03

    申请号：JP2004223211

    申请日：2004-07-30

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： GUARINI KATHRYN W ,  LEONG MEIKEI ,  SHI LEATHEN ,  YANG MIN

    IPC: H01L27/12 ,  H01L21/335 ,  H01L21/762 ,  H01L27/08

    CPC classification number: H01L21/76275 ,  H01L21/76267 ,  H01L21/76283

    Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit device which is formed on a SOI(silicon-on-insulator) substrate, which can realize highest performance of a specific device and has different crystal orientations.
    SOLUTION: The integrated circuit device includes at least the SOI substrate which has an upper semiconductor layer of a first crystal orientation and a semiconductor material of a second crystal orientation, the semiconductor material is substantially on the same plane surface and its thickness is the same to that of the upper semiconductor layer, and in an integrated circuit structure, the first crystal orientation is different from the second crystal orientation. The SOI substrate is formed by wafer bonding, ion implantation, and annealing.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种形成在SOI（绝缘体上硅）衬底上的集成电路器件，其能够实现特定器件的最高性能并具有不同的晶体取向。 解决方案：集成电路器件至少包括具有第一晶体取向的上半导体层和第二晶体取向的半导体材料的SOI衬底，半导体材料基本上在同一平面上，其厚度为 与上半导体层相同，在集成电路结构中，第一晶体取向与第二晶体取向不同。 SOI衬底通过晶片接合，离子注入和退火形成。 版权所有（C）2005，JPO＆NCIPI

    Three dimensional cmos integrated circuit having device layer constituted on wafer with different crystal orientation
    5.
    发明专利
    Three dimensional cmos integrated circuit having device layer constituted on wafer with different crystal orientation 审中-公开
    三维CMOS集成电路，具有不同晶体取向的波形上的器件层

    公开(公告)号：JP2005109498A

    公开(公告)日：2005-04-21

    申请号：JP2004282572

    申请日：2004-09-28

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHAN VICTOR ,  GUARINI KATHRYN W ,  LEONG MEIKEI

    IPC: H01L27/08 ,  H01L21/02 ,  H01L21/336 ,  H01L21/68 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/00 ,  H01L27/06 ,  H01L27/085 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

    CPC classification number: H01L21/6835 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2221/68368 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a 3D (3-dimensional) integrating method of manufacturing 3D integrated circuit, in which a pFET is arranged on a crystal surface optimal for this device, and an nFET can be arranged on a crystal surface optimal for this type of device.
    SOLUTION: In a first 3D integrating method, a first semiconductor device is constituted on a semiconductor surface of a first SOI (silicon-on-insulator) substrate, in advance, and a second semiconductor device is constituted on a semiconductor surface of a second SOI substrate in advance. After these two structures have been constituted in advance, these structures are combined mutually, and they are interconnected via a wafer, namely, via a penetration via hole. In a second 3D integrating method, the first semiconductor device is formed, in such a way that a blanket SOI substrate having a first SOI layer of a first crystal orientation is combined at a surface of the wafer, which has been manufactured, in advance and has the second semiconductor device, on a second SOI layer having a crystal orientation different from that of the first SOI layer and the first semiconductor device on the first SOI layer.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种制造3D集成电路的3D（3维）积分方法，其中pFET布置在该器件最佳的晶体表面上，并且nFET可以布置在晶体表面上 最适合这种类型的设备。 解决方案：在第一3D积分方法中，第一半导体器件预先在第一SOI（绝缘体上硅）衬底的半导体表面上构成，并且第二半导体器件构成在半导体表面上 第二SOI衬底。 在预先构成这两个结构之后，这些结构相互组合，并且它们通过晶片，即经由穿透通孔相互连接。 在第二3D积分方法中，第一半导体器件被形成为使得具有第一晶体取向的第一SOI层的覆盖SOI衬底预先在已经制造的晶片的表面上组合，并且 具有第二SOI层，具有不同于第一SOI层的晶体取向和第一SOI层上的第一半导体器件的第二SOI层。 版权所有（C）2005，JPO＆NCIPI

    COMPRESSIVE SIGE <110> GROWTH MOSFET DEVICES
    6.
    发明申请
    COMPRESSIVE SIGE <110> GROWTH MOSFET DEVICES 审中-公开
    压缩信号<110>增长型MOSFET器件

    公开(公告)号：WO2006002410A3

    公开(公告)日：2007-12-06

    申请号：PCT/US2005022643

    申请日：2005-06-21

    Applicant: IBM ,  CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

    Inventor： CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

    IPC: H01L29/04 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/036 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L29/045 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/823807 ,  H01L29/1054

    Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psuedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600ºC and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described comprising the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HC1 acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a RMS roughness of less than 0.1 nm.

    Abstract translation: 描述了用于导电载体的结构和形成方法，其结合了在<110>中具有上表面的Si或SiGe的单晶衬底和SiGe的形貌或外延层，其Ge浓度与衬底的Ge不同，由此使形成层 正在紧张。 描述了一种用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中通过将工具中的温度增加到约600℃并形成含硅气体和锗的Ge形成或外延层的步骤 含气。 描述了一种用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底浸入含有臭氧，稀HF，去离子水，HCl酸和去离子水的一系列浴中，然后在惰性气氛中干燥衬底 以获得不含杂质且RMS小于0.1nm的衬底表面。

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