公开(公告)号：JP2005136410A

公开(公告)日：2005-05-26

申请号：JP2004310704

申请日：2004-10-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEONG MEIKEI ,  REZNICEK ALEXANDER ,  YANG MIN

IPC: H01L21/822 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a hybrid substrate, equipped with semiconductor layers, having different crystal orientations isolated by a conductive or an insulating interface.
SOLUTION: A method of providing a hybrid substrate, equipped with semiconductor layers having different crystal orientations that are isolated by a conductive or an insulating interface formed by employing semiconductor-to-semiconductor direct wafer bonding, is disclosed. The hybrid substrate may also be yielded by a method, employing a direct bonding method which provides an integrated semiconductor structure, in which various CMOSs are constructed on plane directions which enhance the performance of a device.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供配备有通过导电或绝缘界面隔离的不同晶体取向的半导体层的混合基板。 解决方案：提供一种提供混合基板的方法，该混合基板配备有通过采用半导体至半导体直接晶片接合形成的导电或绝缘界面隔离的具有不同晶体取向的半导体层。 也可以通过使用提供集成半导体结构的直接接合方法的方法来产生混合衬底，其中在平面方向上构造各种CMOS，这增强了器件的性能。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：EP1875508A4

公开(公告)日：2009-08-05

申请号：EP06750977

申请日：2006-04-21

Applicant: IBM

Inventor： DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

IPC: H01L29/04

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.

公开(公告)号：EP1779436A4

公开(公告)日：2009-05-13

申请号：EP05790060

申请日：2005-06-20

Applicant: IBM

Inventor： DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

IPC: H01L27/01 ,  H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76

CPC classification number: H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

公开(公告)号：JP2005057284A

公开(公告)日：2005-03-03

申请号：JP2004223211

申请日：2004-07-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GUARINI KATHRYN W ,  LEONG MEIKEI ,  SHI LEATHEN ,  YANG MIN

IPC: H01L27/12 ,  H01L21/335 ,  H01L21/762 ,  H01L27/08

CPC classification number: H01L21/76275 ,  H01L21/76267 ,  H01L21/76283

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit device which is formed on a SOI(silicon-on-insulator) substrate, which can realize highest performance of a specific device and has different crystal orientations.
SOLUTION: The integrated circuit device includes at least the SOI substrate which has an upper semiconductor layer of a first crystal orientation and a semiconductor material of a second crystal orientation, the semiconductor material is substantially on the same plane surface and its thickness is the same to that of the upper semiconductor layer, and in an integrated circuit structure, the first crystal orientation is different from the second crystal orientation. The SOI substrate is formed by wafer bonding, ion implantation, and annealing.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种形成在SOI（绝缘体上硅）衬底上的集成电路器件，其能够实现特定器件的最高性能并具有不同的晶体取向。 解决方案：集成电路器件至少包括具有第一晶体取向的上半导体层和第二晶体取向的半导体材料的SOI衬底，半导体材料基本上在同一平面上，其厚度为 与上半导体层相同，在集成电路结构中，第一晶体取向与第二晶体取向不同。 SOI衬底通过晶片接合，离子注入和退火形成。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005019996A

公开(公告)日：2005-01-20

申请号：JP2004183756

申请日：2004-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  DAINE C BOYD ,  IEONG MEIKEI ,  KANARSKY THOMAS S ,  KEDZIERSKI JAKUB T ,  YANG MIN

IPC: H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor circuit including at least one FinFET device and at least one planer single-gate FET device on a same SOI semiconductor substrate.
SOLUTION: The integrated semiconductor circuit includes a FinFET and a planer single-gate FET located on an embedded insulating layer of a silicon-on-insulator (SOI) substrate. The planer single FET is located on a surface of a patterned top semiconductor layer of the SOI substrate; and the FinFET has a vertical channel perpendicular to the planer single-gate FET. In a method for forming such an integrated circuit, when width of the FinFET active device region is trimmed, a formed resist image and a patterned hard mask are used, and after that the formed resist image and etching are used when thickness of the FET device region is reduced. The trimmed active FinFET device region is formed such that it is perpendicular to the planer single-gate FET device region whose thickness has been reduced.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供在同一SOI半导体衬底上包括至少一个FinFET器件和至少一个平面单栅极FET器件的集成半导体电路。 解决方案：集成半导体电路包括位于绝缘体上硅（SOI）衬底的嵌入式绝缘层上的FinFET和平面单栅极FET。 平面单个FET位于SOI衬底的图案化顶部半导体层的表面上; 并且FinFET具有垂直于平面单栅极FET的垂直沟道。 在形成这种集成电路的方法中，当FinFET有源器件区域的宽度被修整时，使用形成的抗蚀剂图像和图案化的硬掩模，然后在FET器件的厚度时使用所形成的抗蚀剂图像和蚀刻 区域减少。 经修整的有源FinFET器件区域形成为使其垂直于厚度已经减小的平面单栅极FET器件区域。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：EP1875507A4

公开(公告)日：2009-08-05

申请号：EP06740000

申请日：2006-03-30

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  SLEIGHT JEFFREY W ,  YANG MIN

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1207

Abstract: The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

公开(公告)号：EP1794786A4

公开(公告)日：2008-12-24

申请号：EP05785191

申请日：2005-06-21

Applicant: IBM

Inventor： CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

IPC: H01L29/04 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/036 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/045 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/823807 ,  H01L29/1054

Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psuedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600ºC and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described comprising the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HC1 acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a RMS roughness of less than 0.1 nm.

Abstract translation: 描述了一种用于导电载体的结构和形成方法，该结构包括在<110>中具有上表面的Si或SiGe的单晶衬底以及具有不同于衬底的Ge浓度的伪晶体或外延层，由此该伪晶体层 正处于紧张状态。 描述了用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中形成假性或外延层的步骤，通过将工具中的温度提高至约600℃并且将含Si气体和Ge 含有气体。 描述了用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底分别浸入一系列含有臭氧，稀HF，去离子水，HCl酸和去离子水的浴中，接着在惰性气氛中干燥衬底 以获得无杂质且具有小于0.1nm的RMS粗糙度的基材表面。

公开(公告)号：WO2006057645A8

公开(公告)日：2006-08-03

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

Abstract translation: 本发明提供具有增强的电子和空穴迁移率的半导体材料，其包含具有110晶向和双向压缩应变的含有层。 术语“双轴压缩应力”在本文中用于描述由在制造半导体材料期间在含Si层上感应的纵向压缩应力和横向应力引起的净应力。 本发明的另一方面涉及一种形成本发明的半导体材料的方法。 本发明的方法包括提供含硅110层的步骤; 并在含硅110层中产生双轴应变。

公开(公告)号：WO2005124871A2

公开(公告)日：2005-12-29

申请号：PCT/US2005021674

申请日：2005-06-20

Applicant: IBM ,  DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

Inventor： DORIS BRUCE B ,  IEONG MEIKEI ,  NOWAK EDWARD J ,  YANG MIN

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04 ,  H01L29/76

CPC classification number: H01L21/76251 ,  H01L21/76243 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

Abstract translation: 提供了具有用于平面和/或多栅极金属氧化物半导体场效应晶体管（MOSFET）的高迁移率表面的混合衬底。 混合基板具有对于n型器件是最佳的第一表面部分和对于p型器件是最佳的第二表面部分。 由于混合衬底的每个半导体层中的适当的表面和晶片平坦取向，器件的所有栅极被定向在相同的方向上，并且所有沟道都位于高迁移率表面上。 本发明还提供了一种制造混合衬底的方法以及在其上集成至少一个平面或多栅极MOSFET的方法。

公开(公告)号：WO2006002410A3

公开(公告)日：2007-12-06

申请号：PCT/US2005022643

申请日：2005-06-21

Applicant: IBM ,  CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

Inventor： CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

IPC: H01L29/04 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/036 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/045 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/823807 ,  H01L29/1054

Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psuedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600ºC and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described comprising the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HC1 acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a RMS roughness of less than 0.1 nm.

Abstract translation: 描述了用于导电载体的结构和形成方法，其结合了在<110>中具有上表面的Si或SiGe的单晶衬底和SiGe的形貌或外延层，其Ge浓度与衬底的Ge不同，由此使形成层 正在紧张。 描述了一种用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中通过将工具中的温度增加到约600℃并形成含硅气体和锗的Ge形成或外延层的步骤 含气。 描述了一种用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底浸入含有臭氧，稀HF，去离子水，HCl酸和去离子水的一系列浴中，然后在惰性气氛中干燥衬底 以获得不含杂质且RMS小于0.1nm的衬底表面。