公开(公告)号：EP1794786A4

公开(公告)日：2008-12-24

申请号：EP05785191

申请日：2005-06-21

Applicant: IBM

Inventor： CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

IPC: H01L29/04 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/036 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/045 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/823807 ,  H01L29/1054

Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psuedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600ºC and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described comprising the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HC1 acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a RMS roughness of less than 0.1 nm.

Abstract translation: 描述了一种用于导电载体的结构和形成方法，该结构包括在<110>中具有上表面的Si或SiGe的单晶衬底以及具有不同于衬底的Ge浓度的伪晶体或外延层，由此该伪晶体层 正处于紧张状态。 描述了用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中形成假性或外延层的步骤，通过将工具中的温度提高至约600℃并且将含Si气体和Ge 含有气体。 描述了用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底分别浸入一系列含有臭氧，稀HF，去离子水，HCl酸和去离子水的浴中，接着在惰性气氛中干燥衬底 以获得无杂质且具有小于0.1nm的RMS粗糙度的基材表面。

公开(公告)号：EP2050128A4

公开(公告)日：2009-12-23

申请号：EP07813250

申请日：2007-07-24

Applicant: IBM

Inventor： CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

公开(公告)号：EP2024995A4

公开(公告)日：2013-07-03

申请号：EP07797764

申请日：2007-05-25

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L21/764 ,  H01L21/76283

公开(公告)号：EP2108192A4

公开(公告)日：2009-12-30

申请号：EP07855285

申请日：2007-12-20

Applicant: IBM

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/10 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

公开(公告)号：JP2007150293A

公开(公告)日：2007-06-14

申请号：JP2006303411

申请日：2006-11-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RIM KERN ,  ELLIS-MONAGHAN JOHN J ,  ROBERT J PURTELL ,  BRIAN J GREENE ,  CLEMENT H WANN ,  WILLIAM K HENSON ,  WILDMAN HORATIO S

IPC: H01L21/28

CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/84

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a semiconductor structure comprising different species of silicide or germanide positioned in different regions of the semiconductor structure.
SOLUTION: The different species of silicide or germanide is formed on a semiconductor layer and/or a conductor layer. By this invention, by utilizing combination of continuous accumulation of different metals and pattern formation, the different silicide or germanide are formed in the different regions of a semiconductor chip. This method includes a step for providing a Si-including layer or a Ge layer having at least a first region and a second region, a step for forming a first silicide or germanide in one of the first region and the second region, and a step for forming a second silicide or germanide having different composition from the first silicide or germanide in the other region not including the first silicide or germanide. The steps for forming the first and second silicide or germanide are performed continuously or with a single step.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种形成半导体结构的方法，所述半导体结构包括位于半导体结构的不同区域中的不同种类的硅化物或锗化物。 解决方案：在半导体层和/或导体层上形成不同种类的硅化物或锗化物。 通过本发明，通过利用不同金属的连续积累和图案形成的组合，在半导体芯片的不同区域中形成不同的硅化物或锗化物。 该方法包括提供具有至少第一区域和第二区域的含Si的层或Ge层的步骤，在第一区域和第二区域之一中形成第一硅化物或锗化物的步骤，以及步骤 用于在不包括第一硅化物或锗化锗的另一区域中形成具有不同组成的第二硅化物或锗化物与第一硅化物或锗化物。 用于形成第一和第二硅化物或锗化物的步骤连续地或单步进行。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2007112432A3

公开(公告)日：2009-03-26

申请号：PCT/US2007065324

申请日：2007-03-28

Applicant: IBM ,  LIU YAOCHENG ,  GLUSCHENKOV OLEG ,  RIM KERN ,  MADAN ANITA ,  HOLT JUDSON

Inventor： LIU YAOCHENG ,  GLUSCHENKOV OLEG ,  RIM KERN ,  MADAN ANITA ,  HOLT JUDSON

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L21/2022 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

Abstract: Expitaxial substitutional solid solutions of silicon carbon (101 ) can be obtained by an ultra-fast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials (101 ) with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si1-yCy, y

Abstract translation: 可以通过非晶态含碳硅材料的超快速退火获得硅碳（101）的外延替代固溶体。 退火在高于再结晶点的温度下进行，但低于材料的熔点，并且在该温度范围内优选持续小于100毫秒。 退火优选是闪光退火或激光退火。 该方法能够产生具有替代晶格位置的大部分碳原子的外延硅和含碳材料（101）。 该方法在CMOS工艺和其他电子器件制造中特别有用，其中外延Si1-yCy，y <0.1对于应变工程或带隙工程是需要的。

公开(公告)号：WO2004077509A3

公开(公告)日：2004-10-21

申请号：PCT/US2004005020

申请日：2004-02-20

Applicant: IBM ,  KOESTER STEVEN ,  BEYER KLAUS ,  HARGROVE MICHAEL ,  RIM KERN ,  CHAN KEVIN

Inventor： KOESTER STEVEN ,  BEYER KLAUS ,  HARGROVE MICHAEL ,  RIM KERN ,  CHAN KEVIN

IPC: H01L21/762 ,  H01L29/786

CPC classification number: H01L29/7842 ,  H01L21/76224 ,  H01L29/78687

Abstract: A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

Abstract translation: 公开了用于隔离电子设备的结构和用于制造该结构的方法。 电子器件在包括应变Si层下方的SiGe基础层的衬底中进行处理。 隔离结构包括从衬底顶表面向下延伸并穿透SiGe基层的沟槽，在衬底中形成侧壁。 外延Si衬垫被选择性地沉积到沟槽侧壁上，并且随后被热氧化。 沟槽填充有沟槽电介质，其突出于衬底顶表面之上。

公开(公告)号：WO2008014228A3

公开(公告)日：2008-09-04

申请号：PCT/US2007074169

申请日：2007-07-24

Applicant: IBM ,  CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

Inventor： CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

IPC: H01L21/336

CPC classification number: H01L21/823864 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si: C and polishing an etching the Si: C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si: C with sufficiently high substitutional carbon content are inherently non-selective.

Abstract translation: 为了通过向NFET的沟道区施加张力而有效地增加电子迁移率，具有超过1％的替代碳含量的嵌入式硅碳（Si：C）通过过度填充由晶体管栅极结构形成的间隙或沟槽来实现 与Si：C并且在超级大马士革工艺中将Si：C蚀刻到凸起栅极结构的表面或其下方，即使能够沉积的工艺仅在晶体管源极和漏极之上的选定区域中留下Si：C 具有足够高取代碳含量的Si：C本质上是非选择性的。

公开(公告)号：WO2006002410A3

公开(公告)日：2007-12-06

申请号：PCT/US2005022643

申请日：2005-06-21

Applicant: IBM ,  CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

Inventor： CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

IPC: H01L29/04 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/036 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/045 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/823807 ,  H01L29/1054

Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psuedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600ºC and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described comprising the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HC1 acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a RMS roughness of less than 0.1 nm.

Abstract translation: 描述了用于导电载体的结构和形成方法，其结合了在<110>中具有上表面的Si或SiGe的单晶衬底和SiGe的形貌或外延层，其Ge浓度与衬底的Ge不同，由此使形成层 正在紧张。 描述了一种用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中通过将工具中的温度增加到约600℃并形成含硅气体和锗的Ge形成或外延层的步骤 含气。 描述了一种用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底浸入含有臭氧，稀HF，去离子水，HCl酸和去离子水的一系列浴中，然后在惰性气氛中干燥衬底 以获得不含杂质且RMS小于0.1nm的衬底表面。

公开(公告)号：WO2008085686A2

公开(公告)日：2008-07-17

申请号：PCT/US2007088266

申请日：2007-12-20

Applicant: IBM ,  LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed suicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed suicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Abstract translation: 虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。 本发明提供了在放置在半导体衬底上的硅合金表面上提供非合金硅化物的结构和方法。 这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。 此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。