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    Josephson junction memory using vortex modes
    1.
    发明授权
    Josephson junction memory using vortex modes 失效
    约瑟夫逊结记忆使用涡流模式

    公开(公告)号：US3916391A

    公开(公告)日：1975-10-28

    申请号：US50543374

    申请日：1974-09-12

    Applicant: IBM

    Inventor： GUERET PIERRE L

    IPC: G11C11/14 ,  G11C11/44

    CPC classification number: G11C11/44 ,  Y10S505/832

    Abstract: A memory array consists of Josephson junctions arranged in rows and columns of a matrix, each individual junction serving as a storage cell for one bit of information. The junction parameters are chosen such that the junctions, while remaining in their superconducting state can assume either of at least two vortex modes wherein no flux quanta or a certain number of flux quanta can be trapped within the junction. Optimum positioning of the vortex modes is achieved by appropriately shaping the junctions which has the effect of increasing the area(s) of overlap of the vortex modes. Switching between vortex modes for writing and reading of information is achieved by coincidentally applying word and bit currents to the columns and rows of the array, respectively. Switching between vortex modes generates voltage spikes which are detected by reading arrangements which are also disclosed.

    Abstract translation: 存储器阵列由布置在矩阵的行和列中的约瑟夫逊结组成，每个单独的结用作一位信息的存储单元。 连接参数被选择为使得结点在保持超导状态的同时可以采用至少两种涡流模式，其中通量量程或一定数量的通量量子可以在结中被捕获。 通过适当地形成具有增加涡流模式的重叠面积的作用的连接点来实现涡流模式的最佳定位。

    LOW TEMPERATURE TUNNELING TRANSISTOR
    4.
    发明专利
    LOW TEMPERATURE TUNNELING TRANSISTOR 未知

    公开(公告)号：CA1216961A

    公开(公告)日：1987-01-20

    申请号：CA469778

    申请日：1984-12-11

    Applicant: IBM

    Inventor： GRAF VOLKER ,  GUERET PIERRE L ,  MUELLER CARL A

    IPC: H01L29/15 ,  H01L39/22

    Abstract: LOW TEMPERATURE TUNNELING TRANSISTOR The low temperature tunneling transistor comprises a source electrode and a drain electrode, with a semiconductor tunnel channel arranged therebetween. A gate for applying control signals is coupled to the channel. The semiconductor, at low temperatures, behaves like an insulator with a low barrier through which charge carriers can tunnel under the influence of an applied drain voltage. The tunnel current can be controlled by a gate voltage which modifies the barrier height between source and drain thereby changing the tunnel probability.

    BINARY CIRCUITRY INCLUDING SWITCHING ELEMENTS UTILIZING SUPERCONDUCTIVE TUNNELING EFFECTS
    7.
    发明专利
    BINARY CIRCUITRY INCLUDING SWITCHING ELEMENTS UTILIZING SUPERCONDUCTIVE TUNNELING EFFECTS 未知

    公开(公告)号：CA1035042A

    公开(公告)日：1978-07-18

    申请号：CA215640

    申请日：1974-12-10

    Applicant: IBM

    Inventor： BAECHTOLD WERNER ,  GUERET PIERRE L

    IPC: H03K3/38 ,  H03K19/195

    Abstract: Two Josephson gates are connected in series to a low impedance voltage source. Each junction is bridged by a load impedance. The feed voltage is maintained in the order of the gap voltage which corresponds to the voltage drop across a Josephson junction when it is in its single-particle-tunneling state. Therefore, only one out of both Josephson elements can exist in the voltage state at a time, and the other junction is forced to assume the superconducting pair-tunneling state.

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