公开(公告)号：JPS6320837A

公开(公告)日：1988-01-28

申请号：JP13200587

申请日：1987-05-29

Applicant: IBM

Inventor： GRAF VOLKER ,  MOHR THEODOR OSKAR ,  BUCHMANN PETER LEO ,  VETTIGER PETER ,  HOH PETER DAVID

IPC: H01L21/033 ,  H01L21/285 ,  H01L21/311 ,  H01L21/318 ,  H01L21/336 ,  H01L21/338 ,  H01L29/812

公开(公告)号：CA1330193C

公开(公告)日：1994-06-14

申请号：CA594665

申请日：1989-03-23

Applicant: IBM

Inventor： GRAF VOLKER ,  MUELLER CARL A

IPC: C30B23/08 ,  C01G1/00 ,  C23C14/08 ,  C23C14/24 ,  C30B25/02 ,  C30B29/22 ,  H01B12/00 ,  H01B13/00 ,  H01L39/12 ,  H01L39/24

Abstract: This is a method for making layered structures of artificial high-Tc superconductor compounds by which on top of a seed crystal (7) having a lattice structure matching the lattice structure of the superconductor compound to be made, oxide layers (4, 5, 6) of all constituent components are epitaxially grown in a predetermined sequence so as to create a sandwich structure not found in natural crystals. The epitaxial deposition of the constituent components is performed in a reaction chamber having evaporation facilities, inlets for metal-organic gases, and inlets for background gases including oxygen.

公开(公告)号：CA2006266A1

公开(公告)日：1990-09-10

申请号：CA2006266

申请日：1989-12-20

Applicant: IBM

Inventor： GALEUCHET YVAN ,  GRAF VOLKER ,  HEUBERGER WILHELM ,  ROENTGEN PETER

IPC: H01L29/201 ,  C30B29/40 ,  H01L21/20 ,  H01L21/205 ,  H01L21/338 ,  H01L29/775 ,  H01L29/812 ,  H01S5/12 ,  H01S5/223 ,  H01S5/227 ,  H01S5/30 ,  H01S5/32 ,  H01S5/323 ,  H01S5/34 ,  H01S5/40

Abstract: A method, and devices produced therewith, for the epitaxial growth of sub-micron semiconductor structures with at least one crystal plane dependently grown, buried active layer (24) consisting of a III-V compound. The active layer (24) and adjacent embedding layers (23, 25) form a heterostructure produced in a one-step growth process not requiring removal of the sample from the growth chamber inbetween layer depositions. The layers of the structure are grown on a semiconductor substrate (21) having a structured surface exposing regions of different crystal orientation providing growth- and no-growth-planes for the selective growth process. The method allows the production of multiple, closely spaced active layers and of layers consisting of adjoining sections having different physical properties.

公开(公告)号：CA1216961A

公开(公告)日：1987-01-20

申请号：CA469778

申请日：1984-12-11

Applicant: IBM

Inventor： GRAF VOLKER ,  GUERET PIERRE L ,  MUELLER CARL A

IPC: H01L29/15 ,  H01L39/22

Abstract: LOW TEMPERATURE TUNNELING TRANSISTOR The low temperature tunneling transistor comprises a source electrode and a drain electrode, with a semiconductor tunnel channel arranged therebetween. A gate for applying control signals is coupled to the channel. The semiconductor, at low temperatures, behaves like an insulator with a low barrier through which charge carriers can tunnel under the influence of an applied drain voltage. The tunnel current can be controlled by a gate voltage which modifies the barrier height between source and drain thereby changing the tunnel probability.

公开(公告)号：CA2006266C

公开(公告)日：1993-01-12

申请号：CA2006266

申请日：1989-12-20

Applicant: IBM

Inventor： GALEUCHET YVAN ,  GRAF VOLKER ,  HEUBERGER WILHELM ,  ROENTGEN PETER

IPC: H01L29/201 ,  C30B29/40 ,  H01L21/20 ,  H01L21/205 ,  H01L21/338 ,  H01L29/775 ,  H01L29/812 ,  H01S5/12 ,  H01S5/223 ,  H01S5/227 ,  H01S5/30 ,  H01S5/32 ,  H01S5/323 ,  H01S5/34 ,  H01S5/40 ,  H01L21/36

Abstract: A method, and devices produced therewith, for the epitaxial growth of sub-micron semiconductor structures with at least one crystal plane dependently grown, buried active layer (24) consisting of a III-V compound. The active layer (24) and adjacent embedding layers (23, 25) form a heterostructure produced in a one-step growth process not requiring removal of the sample from the growth chamber inbetween layer depositions. The layers of the structure are grown on a semiconductor substrate (21) having a structured surface exposing regions of different crystal orientation providing growth- and no-growth-planes for the selective growth process. The method allows the production of multiple, closely spaced active layers and of layers consisting of adjoining sections having different physical properties.

公开(公告)号：DE3685495D1

公开(公告)日：1992-07-02

申请号：DE3685495

申请日：1986-07-11

Applicant: IBM

Inventor： GRAF VOLKER ,  MOHR THEODOR OSKAR ,  BUCHMANN PETER LEO ,  VETTIGER PETER ,  HOH PETER DAVID

IPC: H01L21/033 ,  H01L21/285 ,  H01L21/311 ,  H01L21/318 ,  H01L21/336 ,  H01L21/338 ,  H01L29/812 ,  H01L21/00 ,  H01L21/28

Abstract: Undercut mask profiles are formed in a semiconductor process by depositing a first plasma CVD nitride layer followed by a second plasma CVD nitride layer at a different excitation frequency, so that the two layer have different etch rates; and patterning and etching the double layer structure to form the desired undercut profile. Method is simple and easy to control and the undercut profile has good temp. stability. The nitride layer are SiNx, SiOxNy or BNx. The gas compsn. for each CVD stage is different, pref. NH3, N2 and SiH4 for the first stage; and N2 and SiH4 for the second stage. The RF frequency is 1-50 MH2 for the first stage and below 100 MHz for the second stage.

公开(公告)号：DE3373167D1

公开(公告)日：1987-09-24

申请号：DE3373167

申请日：1983-12-28

Applicant: IBM

Inventor： GRAF VOLKER ,  GUERET PIERRE LEOPOLD ,  MUELLER CARL ALEXANDER

IPC: H01L29/15 ,  H01L39/22

Abstract: The transistor comprises two electrodes, source (12) and drain (13), with a semiconductor tunnel channel (11) arranged therebetween. A gate (14) for applying control signals is coupled to the channel. The semiconductor, at low temperatures, behaves like an insulator with a low barrier (some meV) through which charge carriers can tunnel under the influence of an applied drain voltage. The tunnel current can be controlled by a gate voltage VG which modifies the barrier height between source and drain thereby changing the tunnel probability.

公开(公告)号：BR8902555A

公开(公告)日：1990-01-23

申请号：BR8902555

申请日：1989-06-02

Applicant: IBM

Inventor： GRAF VOLKER ,  MUELLER CARL ALEXANDER

IPC: C30B23/08 ,  C01G1/00 ,  C23C14/08 ,  C23C14/24 ,  C30B25/02 ,  C30B29/22 ,  H01B12/00 ,  H01B13/00 ,  H01L39/12 ,  H01L39/24 ,  C30B23/02

Abstract: This is a method for making layered structures of artificial high-Tc superconductor compounds by which on top of a seed crystal (7) having a lattice structure matching the lattice structure of the superconductor compound to be made, oxide layers (4, 5, 6) of all constituent components are epitaxially grown in a predetermined sequence so as to create a sandwich structure not found in natural crystals. The epitaxial deposition of the constituent components is performed in a reaction chamber having evaporation facilities, inlets for metal-organic gases, and inlets for background gases including oxygen.