公开(公告)号：US3902055A

公开(公告)日：1975-08-26

申请号：US44913374

申请日：1974-03-07

Applicant: IBM

Inventor： HAIMS MURRAY J ,  HAO HSIEH T ,  LEBIZAY GERALD ,  WEISS ALFRED

IPC: G06F7/501 ,  G06F7/50 ,  G06F7/503 ,  G06F7/506

CPC classification number: G06F7/506 ,  G06F7/501

Abstract: An improvement in binary adder circuits based on a new Boolean algorithm is disclosed. The arrangement permits calculation of the carry from the logical combination of the addend, the EXCLUSIVE OR of the addend and the augend, and the carry of the next preceding stage. The circuit is readily implemented in NOR logic and has particular application in large scale integrated circuits (LSI).

公开(公告)号：US3184613A

公开(公告)日：1965-05-18

申请号：US23144562

申请日：1962-10-18

Applicant: IBM

Inventor： HAIMS MURRAY J

IPC: H03K17/73

CPC classification number: H03K17/73

公开(公告)号：DE2504288A1

公开(公告)日：1975-09-11

申请号：DE2504288

申请日：1975-02-01

Applicant: IBM

Inventor： HAIMS MURRAY J ,  HAO HSIEH TUNG ,  LEBIZAY GERALD ,  WEISS ALFRED

IPC: G06F7/501 ,  G06F7/50 ,  G06F7/503 ,  G06F7/506

Abstract: 1466366 Parallel binary adders INTERNATIONAL BUSINESS MACHINES CORP 5 Feb 1975 [7 March 1974] 4874/75 Heading G4A A parallel binary adder comprises registers 30, 31 which initially respectively store an augend A and an addend B, the quantitites A, B being gated 33, 34 to an exclusive-OR circuit 32 where the quantity A#B is generated and stored (overwriting A) in register 30 via a gate 35, the quantities A#B and B then being gated 37, 38 to a carry generation circuit 36 which generates a carry C therefrom, the quantities A#B and C then being gated 33, 39 to the exclusive-OR circuit 32 which generates the sum S = (A#B)# C therefrom and stores the sum S in register 30. The carry generation circuit 36 may be implemented in AND/OR/NOT logic (Fig. 1, not shown) and operates using Boolean algorithms given in the Specification to simultaneously generate two carries C k-1 , C k from a lower order carry C k+1 . In a second embodiment of the carry generation circuit 36, Fig. 2 (not shown), NOR logic functionally equivalent to Fig. 1 is used to facilitate its implementation as a LSI circuit, the inverses C k-1 , C k of the carries being simultaneously generated from the lower order carry C k+1 .