-
1.发明授权Fluid logic controlled elastic diaphragm switch matrix with cross point shielding 失效流体逻辑控制弹性透光开关矩阵与交叉点屏蔽
公开(公告)号：US3571542A
公开(公告)日：1971-03-23
申请号：US3571542D
申请日：1969-08-12
Applicant: IBM
Inventor： MADDEN THOMAS F , TATE LAWRENCE A , WEISS ALFRED
CPC classification number: F15C3/04 , F15C1/12 , Y10S200/05 , Y10T137/2147
Abstract: The fluid logic controlled elastic diaphragm switch matrix is formed of multiple elastic diaphragms having conductive surface portions in alignment with apertures carried by interspersed rigid sheets with the central elastic diaphragm carrying opposed and insulated conducting surfaces which are grounded when the switch point is open to act as shields. The matrix coordinate input pulses are amplified at each matrix unit to verify proper operation of the switch actuating fluid amplifier.
-
公开(公告)号：US3902055A
公开(公告)日：1975-08-26
申请号：US44913374
申请日：1974-03-07
Applicant: IBM
Inventor： HAIMS MURRAY J , HAO HSIEH T , LEBIZAY GERALD , WEISS ALFRED
Abstract: An improvement in binary adder circuits based on a new Boolean algorithm is disclosed. The arrangement permits calculation of the carry from the logical combination of the addend, the EXCLUSIVE OR of the addend and the augend, and the carry of the next preceding stage. The circuit is readily implemented in NOR logic and has particular application in large scale integrated circuits (LSI).
-
公开(公告)号：US3662348A
公开(公告)日：1972-05-09
申请号：US3662348D
申请日：1970-06-30
Applicant: IBM
Inventor： WEISS ALFRED
CPC classification number: G06F3/16
Abstract: An information system which may be employed as a voice answer back system for assembling and transmitting separate messages on separate output lines. The basic components of the system are a rotating, fixed head sequential memory file, an associative memory, and a group of buffer storage units. Address keys for the words of the messages are obtained from a central processing unit. The rotating memory contains the entire file of message words stored in equal length segments of digital signals and each are identified by a key address. Message words may consist of a number of segments, each having the same key address and further identified by consecutive segment numbers. As the sequential memory is rotated, the key addresses of the segments are compared with the key addresses in the associative memory; and when matches occur, the segments are retained in buffer storages. As each segment of a key address is obtained, the segment is transferred to the output of the system.
Abstract translation: 可以用作语音应答系统的信息系统，用于在单独的输出线上组装和发送单独的消息。 系统的基本组件是旋转，固定头顺序存储器文件，关联存储器和一组缓冲存储单元。 从中央处理单元获得消息字的地址密钥。 旋转存储器包含存储在数字信号的相等长度段中的消息字的整个文件，并且每个都由密钥地址标识。 消息字可以由多个段组成，每个段具有相同的密钥地址，并由连续的段号进一步标识。 当顺序存储器旋转时，段的键地址与关联存储器中的键地址进行比较; 并且当发生匹配时，段被保留在缓冲存储器中。 由于获取了一个密钥地址的每个段，所以该段被传送到系统的输出。
-
公开(公告)号：FR2312072A1
公开(公告)日：1976-12-17
申请号：FR7516536
申请日：1975-05-21
Applicant: IBM
Inventor： KERRIGAN MICHAEL , LEBIZAY GERALD , SORLEY OLIN LOWE MAC , WEISS ALFRED
Abstract: An input-output port control subsystem for use with a computer system having separate source and destination buses incorporated therein. Said system including circuitry for controlling operations of said system and said input/output subsystem, said subsystem including a bidirectional input/output bus for transferring data to and from said system, and separate gating means for selectively connecting said source and destination buses to said bidirectional I/O bus. External devices are connected to said bus thru an adaptor unit which is directly connected to said processing system by appropriate control lines. The input/output subsystem is adapted to operate either under programmed I/O control mode thru the central processing system or in cycle steal mode wherein the I/O devices themselves request cycle steal service time on the I/O bus thru their connected adaptor.
-
Patent Agency Ranking
公开(公告)号：CA1010543A
公开(公告)日：1977-05-17
申请号：CA174799
申请日：1973-06-22
Applicant: IBM
Inventor： STILWELL GEORGE R JR , WEISS ALFRED
Abstract: Parallel tone signals received on a plurality of input lines are digitized. Specific tone combinations represent different data, such as a particular digit or character. A received signal is considered a valid data signal if it is of at least a predetermined minimum time duration. The digitized signals are read into individual shift registers for each line. The length of each shift register is sufficient to store two data signals, each of the predetermined minimum valid time duration. The tone signals received on the input lines are asynchronous and of variable time duration. A multiplexer sequentially reads out the storage registers at a rate which is relatively high compared to the rate at which the digitized signals are entered into the registers. The time-division-multiplexed serial samples from all registers are reconverted to the input tone signals, frequency separated and detected in a multi-frequency receiver, and then applied to a demultiplexer so that the detected signals appear on a plurality of output lines corresponding to the plurality of input lines. Even though each register is completely read out during each sample time by the multiplexer, the last half of the signal stored in a register is recirculated back into the register to be read out as the first half of the register's contents the next time the line is sampled by the multiplexer, thereby eliminating the possibility of the loss of a digit or character during the multiplexing process.
-
公开(公告)号：DE2523372A1
公开(公告)日：1976-01-15
申请号：DE2523372
申请日：1975-05-27
Applicant: IBM
Inventor： KERRIGAN MICHAEL , LEBIZAY GERALD , MACSORLEY OLIN LOWE , WEISS ALFRED
Abstract: An input-output port control subsystem for use with a computer system having separate source and destination buses incorporated therein. Said system including circuitry for controlling operations of said system and said input/output subsystem, said subsystem including a bidirectional input/output bus for transferring data to and from said system, and separate gating means for selectively connecting said source and destination buses to said bidirectional I/O bus. External devices are connected to said bus thru an adaptor unit which is directly connected to said processing system by appropriate control lines. The input/output subsystem is adapted to operate either under programmed I/O control mode thru the central processing system or in cycle steal mode wherein the I/O devices themselves request cycle steal service time on the I/O bus thru their connected adaptor.
-
公开(公告)号：CA1030267A
公开(公告)日：1978-04-25
申请号：CA225414
申请日：1975-04-22
Applicant: IBM
Inventor： LEBIZAY GERALD , KERRIGAN MICHAEL , MAC SORLEY OLIN L , WEISS ALFRED
Abstract: An input-output port control subsystem for use with a computer system having separate source and destination buses incorporated therein. Said system including circuitry for controlling operations of said system and said input/output subsystem, said subsystem including a bidirectional input/output bus for transferring data to and from said system, and separate gating means for selectively connecting said source and destination buses to said bidirectional I/O bus. External devices are connected to said bus thru an adaptor unit which is directly connected to said processing system by appropriate control lines. The input/output subsystem is adapted to operate either under programmed I/O control mode thru the central processing system or in cycle steal mode wherein the I/O devices themselves request cycle steal service time on the I/O bus thru their connected adaptor.
-
公开(公告)号：DE2504288A1
公开(公告)日：1975-09-11
申请号：DE2504288
申请日：1975-02-01
Applicant: IBM
Inventor： HAIMS MURRAY J , HAO HSIEH TUNG , LEBIZAY GERALD , WEISS ALFRED
Abstract: 1466366 Parallel binary adders INTERNATIONAL BUSINESS MACHINES CORP 5 Feb 1975 [7 March 1974] 4874/75 Heading G4A A parallel binary adder comprises registers 30, 31 which initially respectively store an augend A and an addend B, the quantitites A, B being gated 33, 34 to an exclusive-OR circuit 32 where the quantity A#B is generated and stored (overwriting A) in register 30 via a gate 35, the quantities A#B and B then being gated 37, 38 to a carry generation circuit 36 which generates a carry C therefrom, the quantities A#B and C then being gated 33, 39 to the exclusive-OR circuit 32 which generates the sum S = (A#B)# C therefrom and stores the sum S in register 30. The carry generation circuit 36 may be implemented in AND/OR/NOT logic (Fig. 1, not shown) and operates using Boolean algorithms given in the Specification to simultaneously generate two carries C k-1 , C k from a lower order carry C k+1 . In a second embodiment of the carry generation circuit 36, Fig. 2 (not shown), NOR logic functionally equivalent to Fig. 1 is used to facilitate its implementation as a LSI circuit, the inverses C k-1 , C k of the carries being simultaneously generated from the lower order carry C k+1 .
-
公开(公告)号：DE2334566A1
公开(公告)日：1974-02-21
申请号：DE2334566
申请日：1973-07-07
Applicant: IBM
Inventor： STILWELL GEORGE R , WEISS ALFRED
Abstract: Parallel tone signals received on a plurality of input lines are digitized. Specific tone combinations represent different data, such as a particular digit or character. A received signal is considered a valid data signal if it is of at least a predetermined minimum time duration. The digitized signals are read into individual shift registers for each line. The length of each shift register is sufficient to store two data signals, each of the predetermined minimum valid time duration. The tone signals received on the input lines are asynchronous and of variable time duration. A multiplexer sequentially reads out the storage registers at a rate which is relatively high compared to the rate at which the digitized signals are entered into the registers. The time-division-multiplexed serial samples from all registers are reconverted to the input tone signals, frequency separated and detected in a multi-frequency receiver, and then applied to a demultiplexer so that the detected signals appear on a plurality of output lines corresponding to the plurality of input lines. Even though each register is completely read out during each sample time by the multiplexer, the last half of the signal stored in a register is recirculated back into the register to be read out as the first half of the register's contents the next time the line is sampled by the multiplexer, thereby eliminating the possibility of the loss of a digit or character during the multiplexing process.
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.017 seconds)
